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advanced and ever advancing mitsubishi electric mitsubishi 4-bit single-chip microcomputer 4500 series 4551 group users manual mitsubishi electric
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
preface this users manual describes the hardware and instructions of mitsubishis 4551 group cmos 4-bit microcomputer. after reading this manual, the user should have a through knowledge of the functions and features of the 4551 group and should be able to fully utilize the product. the manual starts with specifications and ends with application examples.
this users manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. organization chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. chapter 3 appendix this chapter includes precautions for systems development using the microcomputer, the mask rom confirmation forms (mask rom version), rom programming confirmation forms (one time prom version) and mark specification forms which are to be submitted when ordering. be sure to refer to this chapter because this chapter also includes necessary information for systems development. before using this users manual l l l
4551 group users manual i table of contents chapter 1 hardware description ............................................................................................................................... . 1-3 features ............................................................................................................................... ....... 1-3 pin configuration (top view) ........................................................................................... 1-3 application ............................................................................................................................... . 1-3 block diagram ......................................................................................................................... 1-4 performance overview ....................................................................................................... 1-5 definition of clock and cycle ....................................................................................... 1-5 pin description ........................................................................................................................ 1-6 multifunction ................................................................................................................... 1-7 connections of unused pins ................................................................................... 1-7 port function .................................................................................................................. 1-7 port block diagrams .................................................................................................. 1-8 functional block operations ...................................................................................... 1-10 cpu ............................................................................................................................ ............ 1-10 program memory (rom) ............................................................................................. 1-13 data memory (ram) ...................................................................................................... 1-14 interrupt function ..................................................................................................... 1-15 external interrupts .................................................................................................. 1-18 timers ............................................................................................................................... .. 1-20 watchdog timer ............................................................................................................ 1-24 carrier generating circuit ................................................................................... 1-25 lcd function ................................................................................................................... 1-28 reset function .............................................................................................................. 1-32 voltage drop detection circuit ......................................................................... 1-34 power down function ............................................................................................... 1-35 clock control .............................................................................................................. 1-38 rom ordering method ....................................................................................................... 1-39 list of precautions ............................................................................................................ 1-40 symbol ............................................................................................................................... ......... 1-41 list of instruction function ........................................................................................ 1-42 instruction code table .................................................................................................... 1-44 machine instructions ........................................................................................................ 1-46 control registers .............................................................................................................. 1-60 built-in prom version ........................................................................................................ 1-64 pin configuration (top view) ......................................................................................... 1-64 table of contents
4551 group users manual ii chapter 2 application 2.1 i/o pins ............................................................................................................................... ..... 2-2 2.1.1 i/o ports .......................................................................................................................... 2-2 2.1.2 related registers ............................................................................................................ 2-4 2.1.3 port application examples ............................................................................................. 2-6 2.1.4 notes on use .................................................................................................................. 2-8 2.2 interrupts ............................................................................................................................... .. 2-9 2.2.1 interrupt functions .......................................................................................................... 2-9 2.2.2 related registers .......................................................................................................... 2-10 2.2.3 interrupt application examples .................................................................................... 2-12 2.2.4 notes on use ................................................................................................................ 2-16 2.3 timers ............................................................................................................................... ..... 2-17 2.3.1 timer functions ............................................................................................................. 2-17 2.3.2 related registers .......................................................................................................... 2-17 2.3.3 timer application examples ........................................................................................ 2-20 2.3.4 notes on use ................................................................................................................ 2-24 2.4 carrier generating circuit .................................................................................................. 2-25 2.4.1 carrier functions ........................................................................................................... 2-25 2.4.2 related registers .......................................................................................................... 2-26 2.4.3 carrier wave output application examples ................................................................ 2-28 2.4.4 notes on use ................................................................................................................ 2-32 2.5 lcd function ......................................................................................................................... 2-33 2.5.1 operation description ................................................................................................... 2-33 2.5.2 related registers .......................................................................................................... 2-34 2.5.3 lcd application examples .......................................................................................... 2-36 2.5.4 notes on use ................................................................................................................ 2-38 2.6 power down function .......................................................................................................... 2-39 2.6.1 clock control function .................................................................................................. 2-41 2.6.2 power down function ................................................................................................... 2-41 2.6.3 related register ............................................................................................................ 2-44 2.6.4 power down function application example ............................................................... 2-45 2.6.5 notes on use ................................................................................................................ 2-45 2.7 reset ............................................................................................................................... ........ 2-46 2.7.1 reset circuit .................................................................................................................. 2-46 2.7.2 internal state at reset .................................................................................................. 2-48 2.7.3 voltage drop detection circuit ..................................................................................... 2-49 2.8 oscillation circuit ................................................................................................................ 2-50 2.8.1 oscillation circuit .......................................................................................................... 2-50 2.8.2 oscillation operation .................................................................................................... 2-51 2.8.3 notes on use ................................................................................................................ 2-51 table of contents
4551 group users manual iii chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-4 3.1.4 basic timing diagram ..................................................................................................... 3-5 3.2 typical characteristics ......................................................................................................... 3-6 3.2.1 v dd Ci dd characteristics ................................................................................................. 3-6 3.2.2 v oh Ci oh characteristics (port carr) .......................................................................... 3-9 3.2.3 v ol Ci ol characteristics (ports p0, p1, d 0 Cd 7 , carr, reset ) ............................ 3-10 3.2.4 voltage drop detection circuit temperature characteristics .................................... 3-11 3.3 list of precautions .............................................................................................................. 3-12 3.4 notes on noise ..................................................................................................................... 3-13 3.4.1 shortest wiring length .................................................................................................. 3-13 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................ 3-15 3.4.3 oscillator concerns ....................................................................................................... 3-16 3.4.4 setup for i/o ports ....................................................................................................... 3-17 3.4.5 providing of watchdog timer function by software ................................................... 3-17 3.5 mask rom order confirmation form ............................................................................... 3-18 3.6 rom programming order confirmation form ................................................................ 3-20 3.7 mark specification form ..................................................................................................... 3-21 3.8 package outline ................................................................................................................... 3-22 table of contents
4551 group users manual iv list of figures chapter 1 hardware fig. 1 amc instruction execution example ............................................................................... 1-10 fig. 2 rar instruction execution example ............................................................................... 1-10 fig. 3 registers a, b and register e ........................................................................................ 1-10 fig. 4 tabp p instruction execution example .......................................................................... 1-10 fig. 5 stack registers (sks) structure ....................................................................................... 1-11 fig. 6 example of operation at subroutine call ....................................................................... 1-11 fig. 7 program counter (pc) structure ..................................................................................... 1-12 fig. 8 data pointer (dp) structure ............................................................................................. 1-12 fig. 9 sd instruction execution example .................................................................................. 1-12 fig. 10 rom map of m34551e8 ................................................................................................ 1-13 fig. 11 interrupt address page (addresses 0080 16 to 00ff 16 ) structure ............................ 1-13 fig. 12 ram map ......................................................................................................................... 1-14 fig. 13 program example of interrupt processing ................................................................... 1-16 fig. 14 internal state when interrupt occurs ............................................................................ 1-16 fig. 15 interrupt system diagram ............................................................................................... 1-16 fig. 16 interrupt sequence .......................................................................................................... 1-17 fig. 17 external interrupt circuit structure ................................................................................ 1-18 fig. 18 auto-reload function ....................................................................................................... 1-20 fig. 19 timers structure .............................................................................................................. 1-21 fig. 20 watchdog timer function ................................................................................................ 1-24 fig. 21 program example to enter the ram back-up mode when using the watchdog timer .... 1-24 fig. 22 carrier wave selection register ..................................................................................... 1-25 fig. 23 carrier wave output auto-control by timer 1 .............................................................. 1-27 fig. 24 lcd clock control circuit structure ............................................................................... 1-28 fig. 25 lcd controller/driver structure ...................................................................................... 1-29 fig. 26 lcd ram map ................................................................................................................ 1-30 fig. 27 lcd controller/driver structure ...................................................................................... 1-31 fig. 28 reset release timing ...................................................................................................... 1-32 fig. 29 reset pin input waveform and reset operation ....................................................... 1-32 fig. 30 power-on reset circuit example .................................................................................... 1-32 fig. 31 internal state at reset .................................................................................................... 1-33 fig. 32 voltage drop detection reset circuit ............................................................................. 1-34 fig. 33 voltage drop detection circuit operation waveform .................................................... 1-34 fig. 34 set source and clear source of the p flag ................................................................. 1-36 fig. 35 start condition identified example using the snzp instruction .............................. 1-36 fig. 36 state transition ................................................................................................................ 1-37 fig. 37 clock control circuit structure ....................................................................................... 1-38 fig. 38 ceramic resonator external circuit ............................................................................... 1-39 fig. 39 quartz-crystal oscillator external circuit ...................................................................... 1-39 fig. 40 external 0 interrupt program example ......................................................................... 1-40 fig. 41 pin configuration of built-in prom version ................................................................ 1-64 fig. 42 prom memory map ....................................................................................................... 1-65 fig. 43 flow of writing and test of the product shipped in blank ......................................... 1-65 list of figures
4551 group users manual v chapter 2 application fig. 2.1.1 key input by key scan ................................................................................................. 2-6 fig. 2.1.2 input timing of key scan ............................................................................................. 2-7 fig. 2.2.1 external interrupt operation example ....................................................................... 2-12 fig. 2.2.2 external interrupt setting example ........................................................................... 2-13 fig. 2.2.3 timer 1 constant period interrupt setting example ................................................ 2-14 fig. 2.2.4 timer 2 constant period interrupt setting example ................................................ 2-15 fig. 2.3.1 watchdog timer function ............................................................................................ 2-20 fig. 2.3.2 constant period measurement setting example ..................................................... 2-21 fig. 2.3.3 constant period counter by timer 2 setting example ............................................ 2-22 fig. 2.3.4 watchdog timer setting example .............................................................................. 2-23 fig. 2.4.1 carrier wave selection register ................................................................................ 2-26 fig. 2.4.2 carrier wave auto-control setting example 1 ......................................................... 2-28 fig. 2.4.3 carrier wave auto-control setting example 2 ......................................................... 2-29 fig. 2.4.4 carrier wave output interval setting example ......................................................... 2-30 fig. 2.4.5 carrier wave by software generating example ...................................................... 2-31 fig. 2.5.1 lcd clock control circuit structure ........................................................................... 2-33 fig. 2.5.2 lcd ram map ........................................................................................................... 2-34 fig. 2.5.3 lcd display panel example ...................................................................................... 2-36 fig. 2.5.4 segment assignment example .................................................................................. 2-36 fig. 2.5.5 lcd ram assignment example ............................................................................... 2-36 fig. 2.5.6 initial setting example ................................................................................................ 2-37 fig. 2.6.1 state transition ............................................................................................................ 2-39 fig. 2.6.2 oscillation stabilizing time in each mode ............................................................... 2-40 fig. 2.6.3 start condition identified example ............................................................................ 2-43 fig. 2.6.4 software setting example .......................................................................................... 2-45 fig. 2.7.1 power-on reset circuit example ................................................................................ 2-46 fig. 2.7.2 reset circuit example when the supply voltage rising time exceeds 100 ms .. 2-47 fig. 2.7.3 oscillation stabilizing time after system is released from reset .......................... 2-47 fig. 2.7.4 internal state at reset ................................................................................................ 2-48 fig. 2.7.5 voltage drop detection reset circuit ......................................................................... 2-49 fig. 2.7.6 voltage drop detection circuit operation waveform ............................................... 2-49 fig. 2.8.1 oscillation circuit example connecting ceramic resonator externally .................. 2-50 fig. 2.8.2 oscillation circuit example connecting quartz-crystal externally .......................... 2-50 fig. 2.8.3 structure of clock control circuit .............................................................................. 2-51 chapter 3 appendix fig. 40 external 0 interrupt program example ......................................................................... 3-12 fig. 3.4.1 selection of packages ............................................................................................... 3-13 fig. 3.4.2 wiring for the reset input pin ............................................................................... 3-13 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-14 fig. 3.4.4 wiring for cnv ss pin ............................................................................................... 3-14 fig. 3.4.5 wiring for the v pp pin of the one time prom version ...................................... 3-15 fig. 3.4.6 bypass capacitor across the v ss line and the v cc line ...................................... 3-15 fig. 3.4.7 wiring for a large current signal line ...................................................................... 3-16 fig. 3.4.8 wiring to a signal line where potential levels change frequently ....................... 3-16 fig. 3.4.9 v ss pattern on the underside of an oscillator ....................................................... 3-16 fig. 3.4.10 watchdog timer by software ................................................................................... 3-17 list of figures
4551 group users manual vi list of tabels chapter 1 hardware table selection of system clock .................................................................................................. 1-5 table 1 rom size and pages .................................................................................................... 1-13 table 2 ram size ........................................................................................................................ 1-14 table 3 interrupt sources ............................................................................................................ 1-15 table 4 interrupt request flag, interrupt enable bit and skip instruction .............................. 1-15 table 5 interrupt enable bit function ......................................................................................... 1-15 table 6 interrupt control register ............................................................................................... 1-17 table 7 external interrupt activated condition ......................................................................... 1-18 table 8 external interrupt control register ................................................................................ 1-19 table 9 function related timers ................................................................................................. 1-20 table 10 timer control registers ................................................................................................ 1-22 table 11 carrier generating circuit control register and control flag .................................... 1-26 table 12 duty and maximum number of displayed pixels ..................................................... 1-28 table 13 lcd control registers .................................................................................................. 1-30 table 14 port state at reset ....................................................................................................... 1-33 table 15 functions and states retained at power down ........................................................ 1-35 table 16 return source and return condition .......................................................................... 1-36 table 17 pull-up control register ............................................................................................... 1-36 table 18 clock control register .................................................................................................. 1-38 table 19 product of built-in prom version ............................................................................. 1-64 table 20 programming adapter .................................................................................................. 1-65 chapter 2 application table 2.1.1 pull-up control register pu0 .................................................................................... 2-4 table 2.1.2 lcd control register l2 ............................................................................................ 2-4 table 2.1.3 clock control register mr ........................................................................................ 2-5 table 2.1.4 connections of unused pins ..................................................................................... 2-8 table 2.2.1 interrupt control register v1 ................................................................................... 2-10 table 2.2.2 interrupt control register i1 .................................................................................... 2-11 table 2.3.1 interrupt control register v1 ................................................................................... 2-17 table 2.3.3 timer control register w2 ...................................................................................... 2-18 table 2.3.2 timer control register w1 ...................................................................................... 2-18 table 2.3.4 timer control register w3 ...................................................................................... 2-19 table 2.4.1 carrier wave output control register c2 .............................................................. 2-27 table 2.4.2 carrier wave generating control flag cr ............................................................. 2-27 table 2.5.1 duty and maximum number of displayed pixels ................................................. 2-33 table 2.5.2 lcd control register l1 .......................................................................................... 2-34 table 2.5.3 lcd control register l2 .......................................................................................... 2-35 table 2.5.4 timer control register w3 ...................................................................................... 2-35 table 2.5.5 frame frequency ..................................................................................................... 2-38 table 2.6.1 functions and states retained at ram back-up mode and the clock operating mode .... 2-42 table 2.6.2 return source and return condition ...................................................................... 2-43 table 2.6.3 start condition identification ................................................................................... 2-43 table 2.6.4 clock control register mr ...................................................................................... 2-44 table 2.6.5 pull-up control register pu0 .................................................................................. 2-44 table 2.8.1 maximum value of oscillation frequency and supply voltage ............................ 2-50 list of tables
4551 group users manual vii chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions ....................................................................... 3-3 table 3.1.3 electrical characteristics ........................................................................................... 3-4 list of tables
chapter 1 chapter 1 hardware description features application pin configuration block diagram performance overview pin description functional block operations rom ordering method list of precautions symbol list of instruction function instruction code table machine instructions control registers built-in prom version
hardware 1-2 4551 group users manual memo
4551 group users manual hardware 1-3 description the 4551 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with an 8-bit timer with a reload register, a 14-bit timer which is also used as a watchdog timer, a 4-bit timer with a reload register, a carrier wave output circuit and an lcd control circuit. the mask rom version and built-in prom version of 4551 group are produced as shown in the table below. features l minimum instruction execution time ............................ 1.5 m s (f(x in )=8.0 mhz, v dd =5.0 v, system clock = f(x in )/4) l supply voltage ............................. 2.5 v to 5.5 v (one time prom version) ....................................... 2.2 v to 5.5 v (mask rom version) l system clock switch function ........................................... clock divided by 4 or not divided l lcd control circuit segment output .................................................................. 20 common output ....................................................................4 l carrier wave frequency switch function system clock, system clock/2, system clock/8, system clock/12, system clock/16, system clock/24, h fixed l timers timer 1 ................................ 8-bit timer with a reload register timer 2 ............... 14-bit timer also used as a watchdog timer timer lc ............................. 4-bit timer with a reload register l interrupt ................................................................... 3 sources l voltage drop detection circuit ............................................... 1 l clock generating circuit (ceramic resonance and quartz-crystal oscillation) application remote control transmitter product m34551m4-xxxfp M34551M8-XXXFP (note 1) m34551e8-xxxfp (note 2) rom type mask rom mask rom one time prom package 48p6s-a 48p6s-a 48p6s-a ram size ( 5 4 bits) 280 words 280 words 280 words rom (prom) size ( 5 10 bits) 4096 words 8192 words 8192 words notes 1: under development (aug. 1998) 2: shipped after writing (shipped in blank: m34551e8fp) pin configuration (top view) m34551mx-xxxfp outline 48p6s-a description/features/application/pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 com 2 com 3 seg 0 seg 1 m34551mx-xxxfp seg 11 seg 14 seg 15 seg 9 v ss x out x in p1 0 p1 1 p1 2 p1 3 d 1 d 2 d 3 d 4 p0 0 p0 1 p0 2 p0 3 d 0 reset d 7 /x cout d 6 /x cin carr v dd cnv ss v ss d 5 / int com 1 com 0 seg 10 seg 13 seg 12 p2 3 / seg 19 p2 2 / seg 18 p2 0 / seg 16 p2 1 / seg 17
hardware 1-4 4551 group users manual block diagram block diagram ram 280 words 5 4 bits (lcd ram 20 words 5 4 bits included) rom (note) 4096 to 8192 words 5 10 bits port p0 port p1 4500 series cpu core memory i/o port internal peripheral functions lcd drive control circuit (max. 20 segments 5 4 common) timers timer 1 (8 bits) system clock generating circuit timer 2 (14 bits) x in ? out (main clock) x cin ? cout (sub-clock) remote control carrier wave output register b (4 bits) register a (4 bits) register d (3 bits) register e (8 bits) stack registers sks (8 levels) interrupt stack register sdp(1 level) alu(4 bits) port d port p2 8 4 4 4 timer lc (4 bits) segment output common output 4 20 note: prom 8192 words 5 10 bits
4551 group users manual hardware 1-5 performance overview function 92 1.5 m s (f(x in ) = 8.0 mhz:system clock = f(x in )/4: v dd = 5.0 v) 4096 words 5 10 bits 8192 words 5 10 bits 8192 words 5 10 bits 280 words 5 4 bits (lcd ram 20 words 5 4 bits included) eight independent output ports 4-bit i/o port; each pin is equipped with a pull-up function. 4-bit i/o port; each pin is equipped with a pull-up function. 4-bit input port 1-bit output port (cmos output) 8-bit timer with a reload register 14-bit timer/ fixed dividing frequency timer 4-bit timer with a reload register 3 (one for external and two for timer) 1 level 8 levels (however, only 7 levels can be used when an interrupt is used or the tabp p instruction is executed) 1/2, 1/3 bias 2, 3, 4 duty 4 20 200 k w 5 3 cmos silicon gate 48-pin plastic molded qfp C20 c to 70 c 2.2 v to 5.5 v (one time prom version: 2.5 v to 5.5 v) 2.5 ma (f(x in ) = 8.0 mhz system clock = f(x in )/4, v dd =5 v) 27.5 m a (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 khz, ta=25 c, v dd =5 v) 0.1 m a (at main clock oscillation stop, sub-clock oscillation stop, ta=25 c, v dd =5v) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports timers interrupt subroutine nesting lcd device structure package operating temperature range supply voltage power dissipation (typical value) rom ram d 0 Cd 7 p0 0 Cp0 3 p1 0 Cp1 3 p2 0 Cp2 3 carr timer 1 timer 2/ watchdog timer timer lc sources nesting selective bias value selective duty value common output segment output internal resistor for power supply at active at clock operating at ram back-up m34551m4 m34551m8 m34551e8 output i/o i/o input output definition of clock and cycle l system clock (stck) the system clock is the basic clock for controlling this product. the system clock can be selected by bits 0 and 3 of the clock control register mr as shown in the table below. table selection of system clock l instruction clock (instk) the instruction clock is the standard clock for controlling cpu. the instruction clock is a signal derived from dividing the system clock by 3. the one cycle of the instruction clock is equivalent to the one machine cycle. l machine cycle the machine cycle is the standard cycle required to execute the instruction. note: f(x in )/4 is selected immediately after system is released from reset. register mr mr 3 0 0 1 1 mr 0 0 1 0 1 system clock (stck) f(x in ) f(x cin ) f(x in )/4 f(x cin )/4 performance overview
hardware 1-6 4551 group users manual pin description name power supply ground cnv ss reset input main clock input main clock output output port d output port d/ interrupt input output port d/ sub-clock input output port d/ sub-clock output i/o port p0 i/o port p1 input port p2/ segment output carrier wave output for remote control segment output common output pin v dd v ss cnv ss reset x in x out d 0 Cd 4 d 5 /int d 6 /x cin d 7 /x cout p0 0 Cp0 3 p1 0 Cp1 3 p2 0 /seg 16 C p2 3 /seg 19 carr seg 0 C seg 15 com 0 C com 3 input/output input i/o input output output i/o i/o output i/o i/o i/o output output output function connected to a plus power supply. connected to a 0 v power supply. connect cnv ss to v ss and apply l (0v) to cnv ss certainly. an n-channel open-drain i/o pin for a system reset. a pull-up resistor is built-in this pin. when the watchdog timer causes the system to be reset or the low- supply voltage is detected, the reset pin outputs l level. i/o pins of the main clock generating circuit. a ceramic resonator can be connected between x in pin and x out pin. a feedback resistor is built-in between them. each pin of port d has an independent 1-bit wide output function. the output structure is n-channel open-drain. 1-bit output port. port d 5 is also used as an int input pin. when d 5 /int pin is used as the int input pin, set the output latch to 1. the output structure is n- channel open-drain. each pin of port d has an independent 1-bit output function. ports d 6 and d 7 are also used as pins x cin and x cout for the sub-clock generating circuit, respectively. when pins d 6 /x cin and d 7 /x cout are used as the pins for the sub-clock generating circuit, a 32.0 khz quartz-crystal oscillator can be connected between x cin pin and x cout pin. a feedback resistor is built-in between them. 4-bit i/o port. it can be used as an input port when the output latch is set to 1. the output structure is n-channel open-drain. every pin of the ports has a key-on wakeup function and a pull-up function. 4-bit i/o port. it can be used as an input port when the output latch is set to 1. the output structure is n-channel open-drain. every pin of the ports has a key-on wakeup function and a pull-up function. both functions can be switched by software. 4-bit input port. ports p2 0 Cp2 3 are also used as the segment output pins seg 16 C seg 19 , respectively. carrier wave output pin for remote control transmit. the output structure is the cmos circuit. lcd segment output pins. lcd common output pins. pins com 0 and com 1 are used at 1/2 duty, pins com 0 C com 2 are used at 1/3 duty and pins com 0 Ccom 3 are used at 1/4 duty. pin description
4551 group users manual hardware 1-7 multifunction notes 1: pins except above have just single function. 2: the ports d 5 Cd 7 are the output port and ports p2 0 Cp2 3 are the input ports. connections of unused pins connection connect to v ss , or set the output latch to 0 and open. select ports d 6 and d 7 and connect to v ss , or set the output latch to 0 and open. select port p2 and connect to v ss , or select the segment output function and open. connection open open open set the output latch to 1 and open. open or connect to v ss (note) pin carr seg 0 Cseg 15 com 0 Ccom 3 p0 0 Cp0 3 p1 0 Cp1 3 pin d 0 Cd 4 d 5 /int d 6 /x cin d 7 /x cout p2 0 /seg 16 Cp2 3 / seg 19 pin d 5 d 6 d 7 p2 0 p2 1 p2 2 p2 3 multifunction int x cin x cout seg 16 seg 17 seg 18 seg 19 multifunction d 5 d 6 d 7 p2 0 p2 1 p2 2 p2 3 pin int x cin x cout seg 16 seg 17 seg 18 seg 19 port function port port d port p0 port p1 port p2 control bits 1 4 4 4 control instructions sd rd cld op0a iap0 op1a iap1 iap2 control registers mr pu0 output structure n-channel open-drain n-channel open-drain n-channel open-drain input/ output output (8) i/o (4) i/o (4) input (4) remark pull-up functions key-on wakeup functions pull-up functions (programmable) key-on wakeup functions (programmable) pin d 0 Cd 4 , d 5 /int, d 6 /x cin , d 7 /x cout p0 0 Cp0 3 p1 0 Cp1 3 p2 0 /seg 16 C p2 3 /seg 19 note: in order to connect ports p1 0 Cp1 3 to v ss , turn off their pull-up transistors (pull-up control register pu0 i =0) by software. in order to make these pins open, turn on their pull-up transistors (register pu0 i =1) by software, or turn off their pull-up transistors (register pu0i=0) and set the output latch to 0 ( i = 0, 1, 2, or 3 ). be sure to select the key-on wakeup function and the pull-up function with every one port. (note in order to set the output latch to 0 and make pins open) ? after system is released from reset, a port is in a high-impedance state until the output latch of the port is set to 0 by s oftware. accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. ? to set the output latch periodically is recommended because the value of output latch may change by noise or a program run awa y (caused by noise). (note in order to connect unused pins to v ss or v dd ) ? to avoid noise, connect the unused pins to v ss or v dd at the shortest distance using a thick wire. pin description
hardware 1-8 4551 group users manual port block diagrams d t q key-on wakeup input register a ai iap0 instruction ai pull-up transistor p0 0 ?0 3 (note 1) op0a instruction d t q op1a instruction key-on wakeup input register a ai iap1 instruction pull-up transistor ai p1 0 ?1 3 pu0i (note 1) connected to when selecting seg lcd power supply lcd power supply l2 i register a iap2 instruction lcd control signal p2 0 /seg 16 ?2 3 /seg 19 (note 1) register y decoder sd instruction rd instruction s rq cld instruction d 0 ? 4 register y decoder sd instruction rd instruction s r q cld instruction d 5 /int int input (note 1) (note 1) this symbol represents a parasitic diode. notes 1: i represents bit 0, 1, 2 or 3. 2: mr 2 mr 2 0 1 mr 2 0 1 d 7 /x cout mr 2 d 6 /x cin x cin clock register y decoder sd instruction rd instruction s rq cld instruction register y decoder sd instruction rd instruction s rq cld instruction (note 1) (note 1) pin description
4551 group users manual hardware 1-9 port block diagrams (continued) pin description seg 0 ?eg 15 lcd power supply lcd power supply lcd control signal lcd control signal pch nch com 0 ?om 3 lcd control signal lcd control signal pch lcd control signal lcd control signal nch pch nch lcd power supply lcd power supply lcd power supply this symbol represents a parasitic diode. note: stcr instruction spcr instruction s r q cr flag carrier wave output circuit register c1 tc1a instruction w3 1 timer lc underflow signal f/f w3 0 c2 0 timer 1 underflow signal w2 0 carr to timer 1 carry (note) f/f
functional block operations hardware 1-10 4551 group users manual fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e functional block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4-bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag (cy) register a is a 4-bit register used for arithmetic, transfer, exchange, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (figure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). (cy) (m(dp)) (a) addition alu cy a 3 a 2 a 1 a 0 a 0 cy a 3 a 2 a 1 rar instruction sc instruction rc instruction a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 tab instruction teab instruction tabe instruction tba instruction register b register a register b register a register e fig. 4 tabp p instruction execution example specifying address tabp p instruction p 6 p 5 p 4 p 3 p 2 p 1 p 0 pc h dr 0 dr 2 dr 1 a 3 a 2 a 1 a 0 pc l immediate field value p the contents of register d rom 840 middle-order 4 bits low-order 4 bits register a (4) register b (4) the contents of register a
functional block operations 4551 group users manual hardware 1-11 fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; ? branching to an interrupt service routine (referred to as an interrupt service routine), ? performing a subroutine call, or ? executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used when using an interrupt service routine or when executing a table reference instruction. accordingly, be careful not to stack over when performing these operations together. the contents of registers sks are destroyed when 8 levels are exceeded. the register sk nesting level is pointed automatically by 3- bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an interrupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and register b just before an interrupt until returning to the original routine. multiple interrupts cannot be used. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table reference instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. returning to the bm instruction execution address with the rt instruction, and the bm instruction is equivalent to the nop instruction. (sp) 0 (sk 0 ) 0001 16 (pc) sub1 main program 0002 16 nop address 0000 16 nop 0001 16 bm sub1 subroutine sub1 : nop rt (pc) (sk 0 ) (sp) 7 note: sk 0 sk 1 sk 2 sk 3 sk 4 sk 5 sk 6 sk 7 (sp) = 0 (sp) = 1 (sp) = 2 (sp) = 3 (sp) = 4 (sp) = 5 (sp) = 6 (sp) = 7 program counter (pc) executing the return or table reference instruction executing the subroutine call or table reference instruction stack pointer (sp) points 7 at reset or returning from ram back-up mode. it points 0 by executing the first bm instruction, and the contents of program counter is stored in sk 0 . when the bm instruction is executed after eight stack registers are used ((sp) = 7), (sp) = 0 and the contents of sk 0 is destroyed.
functional block operations hardware 1-12 4551 group users manual fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which specifies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, register x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd or rd instruction (figure 9). z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 data pointer (dp) register z (2) register x (4) register y (4) specifying ram digit specifying ram file specifying ram file group p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 program counter (pc) pc h specifying page pc l specifying address p 6 01 01 1 set specifying bit position port d output latch register y (4) d 5 d 4 d 0 d 6 d 7
functional block operations 4551 group users manual hardware 1-13 program memory (rom) 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. figure 10 shows the rom map of m34551e8. table 1 rom size and pages product m34551m4 m34551m8 m34551e8 rom size ( 5 10 bits) 4096 words 8192 words 8192 words pages 32 (0 to 31) 64 (0 to 63) 64 (0 to 63) a top part of page 1 (addresses 0080 16 to 00ff 16 ) is reserved for interrupt addresses (figure 11). when an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. when using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. page 2 (addresses 0100 16 to 017f 16 ) is the special page for subroutine calls. subroutines written in this page can be called from any page with the 1-word instruction (bm). subroutines extending from page 2 to another page can also be called with the bm instruction when it starts on page 2. rom pattern (bits 7 to 0) of all addresses can be used as data areas with the tabp p instruction. fig. 10 rom map of m34551e8 90 87654321 interrupt address page 0000 16 0080 16 017 f 16 subroutine special page 007 f 16 00 ff 16 0100 16 1 fff 16 0180 16 page 1 page 2 page 0 page 3 page 63 0 fff 16 page 31 fig. 11 interrupt address page (addresses 0080 16 to 00ff 16 ) structure 90 87654321 external 0 interrupt address 0080 16 0084 16 timer 1 interrupt address timer 2 interrupt address 0086 16 00ff 16
functional block operations hardware 1-14 4551 group users manual data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram. also, be sure to set a value to the data pointer certainly when returning from power down. ram includes the area corresponding to the lcd. a segment is turned on automatically when 1 is written in the bit corresponding to the segment. table 2 shows the ram size. figure 12 shows the ram map. table 2 ram size product m34551m4 m34551m8 m34551e8 ram size 280 words 5 4 bits (1120 bits) register y register z register x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 7 ram 280 words 5 4 bits (1120 bits) 23 615 280 words 012 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 the area marked ?(z = 1, x = 0 to 2, y = 0 to 7) is not a memory area. the numbers in the shaded area indicate the corresponding segment output pin numbers. notes 1: 2: fig. 12 ram map
functional block operations 4551 group users manual hardware 1-15 interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. ? interrupt enable flag (inte) = 1 (interrupt enabled) ? interrupt enable bit = 1 (interrupt request occurrence enabled) ? an interrupt activated condition is satisfied (request flag = 1) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every interrupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bits (v1 0 Cv1 3 ) use an interrupt enable bit of interrupt control register v1 to select the corresponding interrupt request or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; ? an interrupt occurs, or ? the next instruction is skipped with a skip instruction. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its interrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources priority level 1 2 3 interrupt address address 0 in page 1 address 4 in page 1 address 6 in page 1 interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt activated condition level change of int pin timer 1 underflow timer 2 underflow table 4 interrupt request flag, interrupt enable bit and skip instruction interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt skip instruction snz0 snzt1 snzt2 request flag exf0 t1f t2f enable bit v1 0 v1 2 v1 3 table 5 interrupt enable bit function skip instruction invalid valid interrupt enable bit 1 0 occurrence of interrupt request enabled disabled
functional block operations hardware 1-16 4551 group users manual ?program counter (pc) ........................................................ each interrupt address ?stack register (sk) .......... the address of main routine to be executed when returning ?interrupt enable flag (inte) ........................................................... 0 (interrupt disabled) ?interrupt request flag (only the flag for the current interrupt source) ........................................................................................... 0 ?data pointer, carry flag, registers a and b, skip flag ...... stored in the interrupt stack register (sdp) automatically fig. 13 program example of interrupt processing (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as follows (figure 14). ? program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). ? interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. ? interrupt request flag only the request flag for the current interrupt source is cleared to 0. ? data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is executed after a branch to a sequence for storing data into stack register is performed. write the branch instruction to an interrupt service routine at an interrupt address. use the rti instruction to return to main routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning to the main routine. (refer to figure 13) fig. 14 internal state when interrupt occurs fig. 15 interrupt system diagram ei rti interrupt service routine interrupt occurs interrupt is enabled main routine : interrupt enabled state : interrupt disabled state t1f v1 2 exf0 v1 0 address 4 in page 1 address 0 in page 1 t2f v1 3 address 6 in page 1 timer 1 underflow request flag (state retained) enable bit enable flag activated condition int pin (l ? h or h ? l input) inte timer 2 underflow
functional block operations 4551 group users manual hardware 1-17 (6) interrupt control register l interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. table 6 interrupt control register v1 3 v1 2 v1 1 v1 0 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit 0 1 0 1 0 1 0 1 interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w note: r represents read enabled, and w represents write enabled. (7) interrupt sequence interrupts occur only when the respective inte flag, interrupt enable bits (v1 0 Cv1 3 ), and interrupt request flags (exf0, t1f, t2f) are 1. the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (refer to figure 16). fig. 16 interrupt sequence the address is stacked to the last cycle. this interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. 2 to 3 machine cycles (note 1, 2) software starts from the interrupt address. flag cleared interrupt enabled state ei instruction execution cycle interrupt enable flag (inte) retaining level for 4 cycles or more of stck is necessary. interrupt disabled state exf0 flag t1f, t2f flags int pin external interrupt timer 1 and timer 2 interrupts interrupt activated condition is satisfied. l when an interrupt request flag is set after its interrupt is enabled 1 machine cycle system clock (stck) ? ? ? ? ? ? ? ? notes 1: 2:
functional block operations hardware 1-18 4551 group users manual external interrupts an external interrupt request occurs when a valid waveform (= waveform causing the external 0 interrupt) is input to an interrupt input pin (edge detection). the external 0 interrupt can be controlled with the interrupt control register i1. table 7 external interrupt activated condition name external 0 interrupt input pin d 5 /int valid waveform falling waveform (h ? l) rising waveform (l ? h) valid waveform selection bit (i1 2 ) 0 1 fig. 17 external interrupt circuit structure one-sided edge detection circuit exf0 i1 2 d 5 /int 0 1 skip snzi0 instruction external 0 interrupt falling rising
functional block operations 4551 group users manual hardware 1-19 (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to 1 when a valid waveform is input to d 5 /int pin. the valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with the skip instruction. the d 5 /int pin need not be selected the external interrupt input int function or the normal output port d 5 function. however, the exf0 flag is set to 1 when a valid waveform output from port d 5 is input to int pin even if it is used as an output port d 5 . l external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to d 5 /int pin. the valid waveform can be selected from rising waveform or falling waveform. an example of how to use the external 0 interrupt is as follows. select the valid waveform with the bit 2 of register i1. clear the exf0 flag to 0 with the snz0 instruction. a set the nop instruction for the case when a skip is performed with the snz0 instruction. ? set both the external 0 interrupt enable bit (v1 0 ) and the inte flag to 1. the external 0 interrupt is now enabled. now when a valid waveform is input to the d 5 /int pin, the exf0 flag is set to 1 and the external 0 interrupt occurs. (2) external interrupt control register l interrupt control register i1 register i1 controls the valid waveform for the external 0 interrupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. table 8 external interrupt control register notes 1: r represents read enabled, and w represents write enabled. 2: depending on the input state of d 5 /int pin, the external interrupt request flag exf0 may be set to 1 when the contents of i1 2 is changed. accordingly, set a value to bit 2 of register i1 and execute the snz0 instruction to clear the exf0 flag after executing at least one instruction. i1 3 i1 2 i1 1 i1 0 not used interrupt valid waveform for int pin selection bit (note 2) not used not used 0 1 0 1 0 1 0 1 this bit has no function, but read/write is enabled. falling waveform (l level of int pin is recognized with the snzi0 instruction) rising waveform (h level of int pin is recognized with the snzi0 instruction) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. interrupt control register i1 r/w at reset : 0000 2 at power down : state retained
functional block operations hardware 1-20 4551 group users manual timers the 4551 group has the following timers. l programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set value n. when it underflows (count to n + 1), a timer interrupt request flag is set to 1, new data is loaded from the reload register, and count continues (auto-reload function). l fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency dividing ratio (n). an interrupt request flag is set to 1 every n count of a count pulse. fig. 18 auto-reload function the 4551 group timer consists of the following circuits. ? prescaler : frequency divider ? timer 1 : 8-bit programmable timer ? timer 2 : 14-bit fixed dividing frequency timer ? timer lc : 4-bit programmable timer (timers 1 and 2 have the interrupt function, respectively) table 9 function related timers prescaler, timer 1, timer 2 and timer lc can be controlled with the timer control registers w1, w2 and w3. each function is described below. count source ? instruction clock (instck) ? prescaler output (orclk) ? carrier generating circuit output (carry, carry/2) ? prescaler output (orclk) ? f(x cin ) ? bit 3 of timer 2 ? system clock (stck) structure frequency divider 8-bit programmable binary down counter 14-bit fixed dividing frequency 4-bit programmable binary down counter circuit prescaler timer 1 timer 2 timer lc use of output signal ? timer 1 and 2 count sources ? timer 1 interrupt ? port carr output control ? timer 2 interrupt ? divider for lcd ? watchdog timer ? divider for lcd ? carrier output frequency dividing ratio 4, 8 1 to 256 16384 1 to 16 control register w1 w1 w2 w2 w3 ff 16 n 00 16 n : counter initial value count starts reload reload 1st underflow 2nd underflow n+1 count n+1 count time an interrupt occurs or a skip instruction is executed. timer 1 interrupt request flag the contents of counter ? ?
functional block operations 4551 group users manual hardware 1-21 fig. 19 timers structure frequency dividing circuit (divided by 3) x in x cin timer 1 interrupt t1f instck orclk carrier wave output control frequency dividing circuit (divided by 4) reload register r1 (8) timer 1 (8) register b register a (t1ab) (tab1) (note 1) 0 1 w2 0 mr0 0 1 w1 1 , w1 0 00,01 10 11 1/4 1/8 w1 3 0 1 0 1 w1 2 prescaler orclk mr 3 0 1 (note 2) 1 2 stck carry count source is stopped by setting to 0. when the t1ab instruction is executed after setting w2 0 to 1, data is written only to reload register r1. when the contents of w2 3 changes from 0 to 1, the count value of timer 2 is initialized. timer 2 1 2 timer lc (4) reload register rlc (4) lcd clock count source orclk timer 2 interrupt t2f count source w2 3 0 1 w2 2, w2 1 00 01 not available q r s wef reset signal wrst instruction system reset to port carr 10,11 (note 1) 0 1 w3 0 1 0 w3 1 1 03 25 47 69 81213 10 11 stck q d t wdf (note 3) notes 1: 2: 3:
functional block operations hardware 1-22 4551 group users manual table 10 timer control registers prescaler control bit prescaler dividing ratio selection bit timer 1 count source selection bits timer control register w1 w1 3 w1 2 w1 1 w1 0 at reset : 0000 2 at power down : 0000 2 0 1 0 1 r/w stop (prescaler state initialized) operating instruction clock (instck) divided by 4 instruction clock (instck) divided by 8 count source prescaler output (orclk) carrier output (carry) carrier output divided by 2 (carry/2) w1 1 0 0 1 1 w1 0 0 1 0 1 timer control register w2 at reset : 1000 2 at power down : C C C 0 2 r/w 0 1 f(x cin ) prescaler output (orclk) w2 3 w2 2 w2 1 w2 0 timer 2 count source selection bit timer 2 count value selection bits timer 1 control bit w2 2 0 0 1 1 w2 1 0 1 0 1 count source underflow occur every 2 14 count underflow occur every 2 13 count not available not available stop (timer 1 state retained) operating 0 1 timer control register w3 at reset : 00 2 at power down : state retained r/w 0 1 0 1 bit 3 of timer 2 is output (timer 2 count source divided by 16) system clock (stck) stop (timer lc state retained) operating w3 1 w3 0 timer lc count source selection bit timer lc control bit note: r represents read enabled, and w represents write enabled. C represents state retained. (1) timer control registers l timer control register w1 register w1 controls the count source of timer 1, the frequency dividing ratio and count operation of prescaler. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. l timer control register w2 register w2 controls the count operation of timer 1 and count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. l timer control register w3 register w3 controls the count operation and count source of timer lc. set the contents of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the contents of register w3 to register a.
functional block operations 4551 group users manual hardware 1-23 (2) precautions note the following for the use of timers. l prescaler stop the prescaler operation to change its frequency dividing ratio. l count source stop timer 1 or timer lc counting to change its count source. when timer 2 count source changes from f(x cin ) to orclk (w2 3 = 0 ? w2 3 = 1), the count value of timer 2 is initialized. however, when timer 2 count source changes from orclk to f(x cin ) (w2 3 = 1 ? w2 3 = 0) or the same count source is set again (w2 3 = 0 ? w2 3 = 0 or w2 3 = 1 ? w2 3 = 1), the count value of timer 2 is not initialized. l timer 2 timer 2 has the watchdog timer function (wdt). when timer 2 is used as the wdt, note that the processing to initialize the count value and the execution of the wrst instruction. l reading the count value stop the prescaler and then execute the tab1 instruction to read timer 1 data. l writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. (3) prescaler prescaler is a frequency divider. its frequency dividing ratio can be selected. the count source of prescaler is the instruction clock (instck). use the bit 2 of register w1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. when the bit 3 of register w1 is cleared to 0, prescaler is initialized, and the output signal (orclk) stops. (4) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload register (r1). when timer 1 stops, data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. when timer 1 is operating, data can be set only in the reload register (r1) with the t1ab instruction. when setting the next count data to reload register r1 while timer 1 is operating, be sure to set data before timer 1 underflows. timer 1 starts counting after the following process; set data in timer 1, select the count source with bits 0 and 1 of register w1, a set the bit 0 of register w2 to 1. once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes 0), the timer 1 interrupt request flag (t1f) is set to 1, new data is loaded from reload register r1, and count continues (auto- reload function). when a value set in reload register r1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). data can be read from timer 1 to registers a and b. stop counting and then execute the tab1 instruction to read its data. (5) timer 2 (interrupt function) timer 2 is a 14-bit binary down counter. timer 2 starts counting after the following process; select the count source with the bit 3 of register w2, and the clock as a count source is supplied. timer 2 stops counting and its count value is retained when supply of a clock as a count source stops. timer 2 is initialized at reset and when the count source changes from f(x cin ) (w2 3 =0) to orclk (w2 3 =1). the count value to set the timer 2 interrupt request flag (t2f) to 1 can be selected from every 8192 count or every 16384 count with bits 1 and 2 of register w2. the count source signal divided by 16 is output from timer 2. timer 2 can be used as a counter for clock in the clock operating mode (pof instruction executed). (6) timer lc timer lc is a 4-bit binary down counter with the timer lc reload register (rlc). data can be set simultaneously in timer lc and the reload register (rlc) with the tlca instruction. timer lc starts counting after the following process; set data in timer lc, select the count source with the bit 1 of register w3, a set the bit 0 of register w3 to 1. timer lc is the timer for lcd clock generating. also, it can be used as the multi-carrier generator by setting the bit 1 of register w3 to 1 and selecting the system clock (stck) as a count source. when the multi-carrier generator is selected, the waveform which is the timer lc underflow signal divided by 2 can be output as a carrier wave from port carr. at this time, stop the carrier generating circuit and lcd control circuit. when the multi-carrier generator (duty ratio: 1/2 fixed) is used, the enable/stop of the carrier wave output from port carr can be set by the stop of timer lc or the carrier wave output auto-control function by timer 1. (7) timer interrupt request flags (t1f and t2f) each timer interrupt request flag is set to 1 when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1 and snzt2). use the interrupt control register v1 to select an interrupt or a skip instruction. an interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction.
functional block operations hardware 1-24 4551 group users manual watchdog timer watchdog timer provides a method to reset the system when a program runs wild. watchdog timer consists of timer 2, watchdog timer enable flag (wef), and watchdog timer flag (wdf). when the wrst instruction is executed after system is released from reset, the wef flag is set to 1. at this time, the watchdog timer starts operating. when the wef flag is set to 1, it cannot be cleared to 0 until system reset is performed. also, when the wrst instruction is not executed once, watchdog timer does not operate because the wef flag retains 0. when the watchdog timer is operating, the wdf flag is set to 1 every time the bit 12 of timer 2 is cleared from 1 to 0. this means that count is performed 8192 times. when the bit 12 of timer 2 is cleared from 1 to 0 while the wdf flag is set to 1, the internal reset signal is generated and system reset is performed. the wdf flag can be cleared to 0 with the wrst instruction. in the ram back-up mode, though timer 2 count operation stops, its count value is retained and the wdf flag is initialized. in the clock operating mode, timer 2 count operation is continued and the wdf flag is initialized. when using the watchdog timer, execute the wrst instruction at a certain cycle which consists of timer 2s 8191 counts or less to keep the microcomputer operation normal. fig. 20 watchdog timer function fig. 21 program example to enter the ram back-up mode when using the watchdog timer the contents of the wdf flag are initialized in the ram back-up mode. if the wdf flag is set to 1 at the same time that the microcomputer enters the ram back-up mode, system reset may be performed. when using the watchdog timer and the ram back-up mode, initialize the wdf flag with the wrst instruction just before the microcomputer enters the ram back-up mode (refer to figure 21). pof2 epof ; pof instruction execution enabled (ram back-up mode) oscillation stop wrst ; clear wdf flag value of timer 2 internal reset signal wrst instruction execution system reset wrst instruction execution wef flag 3fff 16 0000 16 wdf flag ? ? ? ? ? ?
functional block operations 4551 group users manual hardware 1-25 carrier generating circuit the 4551 group has a carrier generating circuit that generates the transfer waveform by dividing the system clock (stck) for each remote control carrier wave. each carrier waveform can be output by setting the carrier wave selection register (c1). also, timer 1 can auto-control the carrier wave output from port carr by setting the carrier wave output control register (c2). fig. 22 carrier wave selection register duty frequency carrier wave register c1 setting value no carrier wave ??fixed c1 0 c1 1 c1 2 1/4 1/2 1/2 1/3 1/2 output waveform stck/24 stck/16 stcr instruction spcr instruction c1 3 stck/12 stck/8 stck 1/4 1/2 1/2 1/3 1/2 (at reset: 0 1 1 1 2 , at power down: 0 1 1 1 2 , w) carrier wave selection register c1 stck/2 no available ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0001 0010 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 0110 1110 1111 ? ? note:??represents write enabled.
functional block operations hardware 1-26 4551 group users manual table 11 carrier generating circuit control register and control flag c2 0 auto-control output by timer 1 is invalid auto-control output by timer 1 is valid carrier wave output auto-control bit 0 1 at reset : 0 2 carrier wave output control register c2 at power down : 0 2 w cr carrier wave generating stop (spcr instruction) carrier wave generating start (stcr instruction) carrier wave generating control 0 1 at reset : 0 2 carrier wave generating control flag cr at power down : 0 2 w note: w represents write enabled. (1) carrier generating circuit related registers l carrier wave selection register c1 each carrier waveform can be selected by setting the register c1. set the contents of this register through register a with the tc1a instruction. l carrier wave output control register c2 timer 1 can auto-control the output enable interval and the output disable interval of the carrier wave output from port carr by setting the register c2. set the contents of this register through register a with the tc2a instruction. the setting of the output enable/disable interval is described below. validate the carrier wave output auto-control function (c2 0 =1). select the carrier wave or the carrier wave divided by 2 as the timer 1 count source. a set the count value (the output enable interval of carrier wave from port carr) to timer 1. ? operate timer 1 (w2 0 =1). ? operate the carrier generating circuit (stcr instruction executed). ? set the next count value (the output disable interval of carrier wave from port carr) to reload register r1 before timer 1 underflow occurs. the carrier wave is output from port carr until the first timer 1 underflow occurs. the output of the carrier wave from port carr is disabled and the next count value is loaded from reload register r1 to timer 1 by the first timer 1 underflow. then, the output of carrier wave is disabled until the second timer 1 underflow. also, the next enable interval of the carrier wave output can be set by setting the third count value to timer 1 reload register before the second timer 1 underflow occurs. if the carrier wave output auto-control function is invalidated (c2 0 =0) while the carrier wave output is auto- controlled, the output of port carr retains the state when the auto-control is invalidated regardless of timer 1 underflow. this state can be terminated by timer 1 stop (w2 0 =0). when the carrier wave output auto-control function is validated (c2 0 =1) again after it is invalidated (c2 0 =0), the auto- control of carrier wave output is started again when the next timer 1 underflow occurs. (2) carrier wave generating control flag (cr) the cr flag is used to control the carrier wave generating operation of the carrier generating circuit. the cr flag is 1 and the carrier wave generating is started by executing the stcr instruction. the cr flag is 0 and the carrier wave generating is stopped by executing the spcr instruction. the cr flag is 0 at system reset. (3) note on the carrier generating circuit stop in order to stop the carrier wave which has the cycle longer than that of the instruction clock with the spcr instruction, stop it at the point when the carrier wave outputs l level in the spcr instruction execution cycle. if this condition is not satisfied, the last h output interval of carrier wave is shortened. (4) notes when using the carrier wave output auto-control function l execute the stcr instruction after setting the timer 1 and register c2 in order to start the carrier generating circuit operation. l stop the timer 1 (w2 0 =0) after stopping the carrier generating circuit (spcr instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. l if the carrier wave output auto-control function is invalidated (c2 0 =0) while the carrier wave output is auto-controlled, the output of port carr retains the state when the auto- control is invalidated regardless of timer 1 underflow. this state can be terminated by timer 1 stop (w2 0 =0). when the carrier wave output auto-control function is validated (c2 0 =1) again after it is invalidated (c2 0 =0), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. however, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. l use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto- control function is selected. if the orclk is used as the count source, a hazard may occur in port carr output because orclk is not synchronized with the carrier wave. l when no carrier wave is selected with register c1 ((c1 3 c1 2 c1 1 c1 0 ) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function.
functional block operations 4551 group users manual hardware 1-27 fig. 23 carrier wave output auto-control by timer 1 timer 1 underflow port carr output (c2 0 ) ? 0 register c2 0 (c2 0 ) ? 1 (c2 0 ) ? 0 (c2 0 ) ? 1 a b c set the interval ??to timer 1. set the interval ??to reload register r1. set the interval ?? to reload register r1. set the interval ??to reload register r1. d timer 1 underflow port carr output (c2 0 ) ? 1 carrier wave output start timer 1 start carrier wave output start ? ? ? ? ? ? ? ? ? ?
functional block operations hardware 1-28 4551 group users manual lcd function the 4551 group has an lcd (liquid crystal display) controller/ driver. when data are set in timer control registers (w2, w3), timer lc, lcd control registers (l1, l2), and lcd ram, the lcd controller/driver automatically reads the display data and controls the lcd display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the lcd. by using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. when the required number of segment pins is 19 or less, pins seg 16 Cseg 19 (4) can be used as input ports p2 0 Cp2 3 . (1) duty and bias there are 3 combinations of duty and bias for displaying data on the lcd. use bits 0 and 1 of lcd control register (l1) to select the proper display method for the lcd panel being used. l 1/2 duty, 1/2 bias l 1/3 duty, 1/3 bias l 1/4 duty, 1/3 bias table 12 duty and maximum number of displayed pixels (2) lcd clock control the lcd clock is determined by the timer 2 count source selection bit (w2 3 ), timer lc control bit (w3 0 ), and timer lc. accordingly, the frequency (f) of the lcd clock is obtained by the following formula. numbers ( to ? ) shown below the formula correspond to numbers in figure 24, respectively. l when using the prescaler output (orclk) as timer 2 count source (w2 3 =1) f = orclk 55 5 l when using the f(x cin ) as timer 2 count source (w2 3 =0) f = f(x cin ) 55 5 [lc: 0 to 15] the frame frequency and frame period for each display method can be obtained by the following formula: frame frequency = (hz) frame period = (s) f: lcd clock frequency 1/n: duty fig. 24 lcd clock control circuit structure duty 1/2 1/3 1/4 used com pins com 0 , com 1 (note) com 0 Ccom 2 (note) com 0 Ccom 3 maximum number of displayed pixels 40 segments 60 segments 80 segments note: leave unused com pins open. 1 16 1 lc + 1 1 2 a ? ? 1 16 1 lc + 1 1 2 a ? ? f n n f note: count source is stopped by clearing to 0. a ? ? timer lc 1/2 1/16 w3 0 0 1 (note) x cin w2 3 0 1 orclk stck w3 1 1 0 lcd clock
functional block operations 4551 group users manual hardware 1-29 fig. 25 lcd controller/driver structure common driver com 0 com 1 com 2 com 3 bias control multiplexer v lc3 control signal seg 0 p2 0 /seg 16 p2 3 /seg 19 multiplexer selector segment driver selector segment driver seg 15 ram ram decoder 1/2, 1/3, 1/4 counter l1 3 l1 2 l1 1 l1 0 lcd on/off control lcd clock (from timer block) selector segment driver ram l2 3 l2 2 l2 1 l2 0 register a ................. ................. ... (note) note: v lc3 =v dd . ... ...
functional block operations hardware 1-30 4551 group users manual (3) lcd ram ram contains areas corresponding to the liquid crystal display. when 1 is written to this lcd ram, the display pixel corresponding to the bit is automatically displayed. (4) lcd drive waveform when 1 is written to a bit in the lcd ram data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lv lc3 l and the display pixel at the cross section turns on. when returning from reset, and in the ram back-up mode, a display pixel turns off because every segment output pin and common output pin becomes v lc3 level (=v dd ). fig. 26 lcd ram map table 13 lcd control registers not used lcd on/off bit lcd duty and bias selection bits lcd control register l1 l1 3 l1 2 l1 1 l1 0 at reset : 0000 2 at power down : state retained 0 1 0 1 r/w this bit has no function, but read/write is enabled off on not available l1 1 0 0 1 1 l1 0 0 1 0 1 duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 lcd control register l2 at reset : 1111 2 at power down : state retained w 0 1 0 1 0 1 0 1 seg 19 p2 3 seg 18 p2 2 seg 17 p2 1 seg 16 p2 0 l2 3 l2 2 l2 1 l2 0 p2 3 /seg 19 pin function switch bit p2 2 /seg 18 pin function switch bit p2 1 /seg 17 pin function switch bit p2 0 /seg 16 pin function switch bit note: r represents read enabled, and w represents write enabled. z x y bit 8 9 10 11 12 13 14 15 com 1 01 2 3 210 3 210 3 210 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 3 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 2 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 1 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 0 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 0 seg 0 seg 0 seg 0 seg 8 seg 17 seg 18 seg 19 seg 16 seg 8 seg 8 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 17 seg 18 seg 19 seg 16 seg 17 seg 18 seg 19 seg 16 seg 17 seg 18 seg 19 seg 16 note: the area marked ? ?is not the lcd display ram.
functional block operations 4551 group users manual hardware 1-31 fig. 27 lcd controller/driver structure 1/2 duty, 1/2 bias: when writing (xx10) 2 to address m (1, 2, 8) in ram. com 1 com 0 seg 16 v lc 3 v lc 1 =v lc 2 v ss v lc 3 v lc 1 =v lc 2 v ss 1 frame (2/f) 1/f on off voltage level (bit 0) com 0 com 1 seg 16 0 1 x x (bit 3) m (1, 2, 8) com 1 seg 16 com 0 seg 16 1/3 duty, 1/3 bias: when writing (x101) 2 to address m (1, 2, 8) in ram. 1 frame (3/f) 1/f on off on com 2 v lc 3 v lc 2 v lc 1 v ss com 1 com 0 seg 16 v lc 3 v lc 2 v lc 1 v ss voltage level (bit 0) com 0 com 1 com 2 seg 16 1 0 1 x (bit 3) m (1, 2, 8) com 2 seg 16 com 1 seg 16 com 0 seg 16 1/4 duty, 1/3 bias: when writing (1010) 2 to address m (1, 2, 8) in ram. 1 frame (4/f) 1/f on off on com 3 com 2 com 1 com 0 seg 16 v lc 3 v lc 2 v lc 1 v ss v lc 3 v lc 2 v lc 1 v ss off voltage level (bit 0) com 0 com 1 com 2 com 3 seg 16 0 1 0 1 (bit 3) m (1, 2, 8) com 3 seg 16 com 2 seg 16 com 1 seg 16 com 0 seg 16 f: lcd clock frequency x: set an arbitrary value. (these bits are not related to set the drive waveform at each duty.)
functional block operations hardware 1-32 4551 group users manual reset function ____________ system reset is performed by applying l level to reset pin for 1 machine cycle or more when the following condition is satisfied; ? the value of supply voltage is the minimum value or more of the recommended operating conditions. ____________ then when h level is applied to reset pin, software starts from address 0 in page 0. fig. 28 reset release timing fig. 29 reset pin input waveform and reset operation (1) power-on reset reset can be automatically performed at power on (power- on reset) by the built-in power-on reset circuit. when the built- in power-on reset circuit is used, the time for the supply voltage to reach the minimum operating voltage must be set to 100 m s or less. if the rising time exceeds 100 m s, connect a capacitor between the reset pin and v ss at the shortest distance, and input l level to reset pin until the value of supply voltage reaches the minimum operating voltage. fig. 30 power-on reset circuit example f(x in ) reset f(x in ) is counted 10757 to 10786 times software start (address 0 in page 0) note: the number of clock cycles depends on the internal state of the microcomputer when reset is performed. (note) ? ? note: keep the value of supply voltage the minimum value or more of the recommended operating conditions. reset software start (address 0 in page 0) reset input 1machine cycle or more = 0.3v dd f(x in ) is counted 10757 to 10786 times (note) 0.85v dd v dd power-on reset circuit output voltage internal reset signal power-on reset pin wef watchdog timer output internal reset signal reset state reset released this symbol represents a parasitic diode. note: applied potential to reset pin must be v dd or less. (note) power-on reset circuit pull-up transistor voltage drop detection circuit
functional block operations 4551 group users manual hardware 1-33 ? program counter (pc) ............................................................................................ address 0 in page 0 is set to program counter. ? interrupt enable flag (inte) ................................................................................... ? power down flag (p) ............................................................................................... ? external 0 interrupt request flag (exf0) ................................................................ ? interrupt control register v1 ................................................................................... ? interrupt control register i1 .................................................................................... ? timer 1 interrupt request flag (t1f) ...................................................................... ? timer 2 interrupt request flag (t2f) ...................................................................... ? watchdog timer flag (wdf) ................................................................................... ? watchdog timer enable flag (wef) ....................................................................... ? timer control register w1 ...................................................................................... ? timer control register w2 ...................................................................................... ? timer control register w3 ...................................................................................... ? clock control register mr ...................................................................................... ? carrier wave selection register c1 ........................................................................ ? carrier wave output control register c2 ................................................................. ? carrier wave generating control flag cr ............................................................... ? lcd control register l1 .......................................................................................... ? lcd control register l2 .......................................................................................... ? pull-up control register pu0 ................................................................................... ? general-purpose register v2 ................................................................................. ? carry flag (cy) ....................................................................................................... ? register a .............................................................................................................. ? register b .............................................................................................................. ? register d .............................................................................................................. ? register e .............................................................................................................. ? data pointer x ........................................................................................................ ? data pointer y ........................................................................................................ ? data pointer z ........................................................................................................ ? stack pointer (sp) .................................................................................................. (2) internal state at reset table 14 shows port state at reset, and figure 31 shows internal state at reset (they are retained after system is released from reset). name d 0 Cd 4 , d 5 /int d 6 /x cin , d 7 /x cout p0 0 Cp0 3 p1 0 Cp1 3 p2 0 /seg 16 Cp2 3 /seg 19 seg 0 Cseg 15 com 0 Ccom 3 carr state high impedance (note 1) h (v dd ) level (note 1) (notes 1, 2) high impedance v lc3 (v dd ) level l (v ss ) level function d 0 Cd 4 , d 5 d 6 , d 7 p0 0 Cp0 3 p1 0 Cp1 3 p2 0 Cp2 3 seg 0 Cseg 15 com 0 Ccom 3 carr notes 1: output latch is set to 1. 2: the pull-up transistor is turned off. table 14 port state at reset the contents of timers, registers, flags and ram except those shown in figure 31 are undefined, so set the initial values to them. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 (interrupt disabled) 0000 0 0 0 0 0 0 0 0 (prescaler stopped) 0 0 0 0 (timer 1 stopped) 0 0 (timer lc stopped) 1000 0111 0 0 (carrier wave output disabled) 0 0 0 0 (lcd off) 1 1 1 1 (port p2 selected) 0000 0000 0 0000 0000 555 0000 0000 55 111 5 represents undefined. fig. 31 internal state at reset 55555555
hardware 1-34 4551 group users manual voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. fig. 32 voltage drop detection reset circuit fig. 33 voltage drop detection circuit operation waveform functional block operations reset pin wef watchdog timer output internal reset signal power-on reset circuit pull-up transistor voltage drop detection circuit v dd reset voltage internal reset signal the microcomputer starts operation after the f(x in ) is counted 10757 to 10786 times.
4551 group users manual hardware 1-35 power down function the 4551 group has 2-type power down functions. l clock operating mode ................................... pof instruction l ram back-up mode .................................... pof2 instruction power down is performed by executing each instruction. above power down functions are different from reset in start conditions. table 15 shows the function and states retained at power down. figure 36 shows the state transition. l return from power down state ............. warm start condition l return from reset state ........................... cold start condition (1) clock operating mode the following functions and states are retained. l ram l reset circuit l x cin Cx cout oscillation l lcd display l timer 2 (2) ram back-up mode the following functions and states are retained. l ram l reset circuit unlike the clock operating mode, all oscillations stop in the ram back-up mode. (3) warm start condition the system returns from the power down state when; l the external wakeup signal is input or the timer 2 underflow occurs in the clock operating mode, or when; l the external wakeup signal is input in the ram back-up mode. in either case, the cpu starts executing the software from address 0 in page 0. in this case, the p flag is 1. (4) cold start condition the cpu starts executing the software from address 0 in page 0 when; l reset pulse is input to reset pin, l reset by watchdog timer is performed, or l reset by the voltage drop detection circuit is performed. in this case, the p flag is 0. table 15 functions and states retained at power down power down ram back-up 5 o o o 5 o 5 o 5 (note 3) o (note 4) 5 o 5 5 o 5 o 5 5 clock operating 5 o o o 5 o 5 o 5 o o o 5 o 5 5 o o o 5 5 function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram port level clock control register mr timer control register w1 timer control registers w2, w3 interrupt control register v1 interrupt control register i1 carrier wave control registers and flag (c1, c2, cr) lcd display function lcd control registers l1, l2 timer lc timer 1 function timer 2 function external 0 interrupt request flag (exf0) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) watchdog timer flag (wdf) watchdog timer enable flag (wef) interrupt enable flag (inte) general-purpose register v2 notes 1: o represents that the function can be retained, and 5 represents that the function is initialized. registers and flags other than the above are undefined at power down, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 111 2 at power down. 3: lcd is turned off. 4: the state of the timer is undefined. functional block operations
hardware 1-36 4551 group users manual (5) identification of the start condition warm start or cold start can be identified by examining the state of the power down flag (p) with the snzp instruction. the warm start condition (timer 2 or external wakeup signal) can be identified by examining the state of t2f flag. fig. 34 set source and clear source of the p flag l set source pof or pof2 instruction executed l clear source reset input s r q powerdown flag p pof instruction or pof2 instruction reset input software start p = 1 t2f = 1 ? ? no yes yes return by external wakeup si g nal return by timer 2 underflow cold start no fig. 35 start condition identified example using the snzp instruction (6) return signal an external wakeup signal or timer 2 interrupt request flag is used to return from the clock operating mode. an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 16 shows the return condition for each return source. (7) port p1 control register l pull-up control register pu0 register pu0 controls the on/off of the port p1 pull-up transistor and the on/off of the key-on wakeup function. set the contents of this register through register a with the tpu0a instruction. in addition, the tapu0 instruction can be used to transfer the contents of register pu0 to register a. table 16 return source and return condition remarks port p0 shares the falling edge detection circuit with port p1. the key-on wakeup function of port p0 is always valid. the only key-on wakeup function of the port p1 bit of which the pull-up transistor is turned on is valid. set all the port using the key-on wakeup function to h level before going into the power down state. the timer 2 interrupt request flag (t2f) can be used only when system returns from the clock operating mode (pof instruction execution). however, if the pof and pof2 instructions are executed while the t2f = 1, its operation is recognized as the return condition and system returns from the clock operating mode. return condition returns by an external falling edge input (h ? l). returns by timer 2 underflow and setting t2f to 1. return source ports p0, p1 timer 2 interrupt request flag external wakeup signal note: p1 pin has the pull-up transistor which can be turned on/off by software. table 17 pull-up control register pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 0000 2 at power down : state retained pull-up control register pu0 r/w pu0 3 pu0 2 pu0 1 pu0 0 note: r represents read enabled, and w represents write enabled. functional block operations
4551 group users manual hardware 1-37 (8) state transition state transition is described using figure 36. fig. 36 state transition functional block operations mr 0 ? 0 b mr 0 ? 1 c mr 1 ? 1 mr 1 ? 0 d k a mr 2 ? 1 mr 0 ? 0 f mr 0 ? 1 g mr 1 ? 1 mr 1 ? 0 h mr 2 ? 0 e mr 2 ? 1 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 (note 2) (note 2) (stabilizing time c ) j f(x in ):stop f(x cin ) : oscillation i (stabilizing time c ) (stabilizing time d ) (stabilizing time d ) b , f c , g d , h b , f c , g d , h a , e a , e b , f c , g d , h b , f c , g d , h a , e (note 2) reset pof execution return input 1 (stabilizing time a ) pof execution return input 1, 2 (stabilizing time a ) pof execution return input 1, 2 (stabilizing time c ) (note 1) clock operating mode pof execution return input 1, 2 (stabilizing time c ) (note 1) f(x in ):stop f(x cin ):stop clock operating mode f(x in ):oscillation f(x cin ):stop system clock; f(x in )/4 mr=(1000 2 ) mr 2 ? 0 f(x in ):oscillation f(x cin ):oscillation f(x in ):oscillation f(x cin ):oscillation f(x in ):stop f(x cin ):oscillation system clock; f(x in )/4 mr=(1100 2 ) system clock; f(x cin )/4 mr=(1101 2 ) system clock; f(x cin )/4 mr=(1111 2 ) f(x in ):oscillation f(x cin ):stop system clock; f(x in ) mr=(0000 2 ) f(x in ):oscillation f(x cin ):oscillation system clock; f(x in ) mr=(0100 2 ) f(x in ):oscillation f(x cin ):oscillation system clock; f(x cin ) mr=(0101 2 ) f(x in ):stop f(x cin ):oscillation system clock; f(x cin ) mr=(0111 2 ) (stabilizing time d ) (note 2) pof2 execution return input 1 (stabilizing time a ) pof2 execution return input 1 (stabilizing time a ) pof2 execution return input 1 (stabilizing time b ) pof2 execution return input 1 (stabilizing time b ) f(x in ):stop f(x cin ):stop ram back-up mode stabilizing time a : an interval required to stabilize the f(x in ) oscillation is automatically generated by hardware. stabilizing time b : an interval required to stabilize the f(x cin ) oscillation is automatically generated by hardware. stabilizing time c : generate an interval required to stabilize the f(x in ) oscillation in state c or g by software at the transition d ? c, d ? g, h ? c, h ? g, j ? c, or j ? g. stabilizing time d : generate an interval required to stabilize the f(x cin ) oscillation in state b, f by software at the transition a ? b, e ? f, a ? f, or e ? b. return input 1: external wakeup signal (p0 0 Cp0 3 , p1 0 Cp1 3 ) return input 2: timer 2 interrupt request flag notes 1. mr 3 =1 ? the microcomputer starts its operation after counting f(x cin ) clock signal 59 to 70 times. mr 3 = 0 ? the microcomputer starts its operation after counting f(x cin ) clock signal 32 to 43 times. 2. when the following 2 conditions are satisfied, the transition a ? e, b ? f, a ? f, c ? f, g ? f represented by can be executed. (1) v dd = 2.2 v to 5.5 v (one time prom version: v dd = 2.5 v to 5.5 v), f(x in ) 1.0 mhz (2) v dd = 4.5 v to 5.5 v, f(x in ) 2.0 mhz a , e mr 2 ? 0 mr 3 ? 0 mr 2 ? 1 mr 3 ? 1 (note 2) mr 2 ? 1 mr 2 ? 0 mr 3 ? 0 mr 3 ? 1 mr 3 ? 1 mr 0 ? 0 mr 3 ? 0 mr 0 ? 1 mr 0 ? 1 mr 0 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 1 ? 0 mr 3 ? 0 mr 1 ? 1 mr 1 ? 0 mr 3 ? 0 mr 1 ? 1 mr 3 ? 1 (stabilizing time c ) (stabilizing time d ) (stabilizing time c )
hardware 1-38 4551 group users manual clock control the clock control circuit consists of the following circuits. l clock generating circuit l control circuit to stop the clock oscillation l system clock (stck) selection circuit l instruction clock (instck) generating circuit l control circuit to return from the power down state fig. 37 clock control circuit structure (1) clock control register l clock control register mr register mr controls the system clock. set the contents of this register through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 18 clock control register system clock (stck) selection bit f(x cin ) oscillation circuit control bit f(x in ) oscillation circuit control bit clock selection bit at reset : 1000 2 at power down : state retained clock control register mr r/w mr 3 mr 2 mr 1 mr 0 mr 0 =0 f(x in ) mr 0 =1 f(x cin ) mr 0 =0 f(x in )/4 mr 0 =1 f(x cin )/4 f(x cin ) oscillation stop, ports d 6 and d 7 selected f(x cin ) oscillation enabled, ports d 6 and d 7 not selected oscillation enabled oscillation stop f(x in ) f(x cin ) 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. functional block operations osc x in x out osc x cin x cout internal clock generating circuit (divided by 3) mr0 r s q r s q pof instruction pof2 instruction mr1 t2f flag falling detected ports p0, p1 reset multiplexer frequency dividing circuit (divided by 4) mr3 0 1 stck instck
4551 group users manual hardware 1-39 fig. 38 ceramic resonator external circuit (2) f(x in ) clock generating circuit clock signal f(x in ) is obtained by externally connecting a ceramic resonator. connect this external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in between pins x in and x out . (3) f(x cin ) clock generating circuit clock signal f(x cin ) is obtained by externally connecting a quartz-crystal oscillator. connect this external circuit to pins x cin and x cout at the shortest distance. a feedback resistor is built in between pins x cin and x cout . rom ordering method please submit the information described below when ordering mask rom. (1) m34551m4-xxxfp mask rom order confirmation form ..............................................................................................1 (2) data to be written into mask rom ? eprom (three sets containing the identical data) (3) mark specification form .................................................... 1 m34551 x in x out rd c in c out externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer? recommended value because constants such as capacitance depend on the resonator. note: fig. 39 quartz-crystal oscillator external circuit m34551 x cin x cout rd c in c out externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the quartz-crystal oscillator manufacturer? recommended value because constants such as capacitance depend on the quartz-crystal oscillator. note: functional block operations/rom ordering method
hardware 1-40 4551 group users manual list of precautions noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; ? connect a bypass capacitor (approx. 0.1 m f) between pins v dd and v ss at the shortest distance, ? equalize its wiring in width and length, and ? use the thickest wire. in the built-in prom version, cnv ss pin is also used as v pp pin. accordingly, when using this pin, connect this pin to v ss through a resistor about 5 k w (connect this resistor to cnv ss / v pp pin as close as possible). prescaler stop the prescaler operation to change its frequency dividing ratio. a count source stop timer 1 or timer lc counting to change its count source. when timer 2 count source changes from f(x cin ) to orclk (w2 3 = 0 ? w2 3 = 1), the count value of timer 2 is initialized. however, when timer 2 count source changes from orclk to f(x cin ) (w2 3 = 1 ? w2 3 = 0) or the same count source is set again (w2 3 = 0 ? w2 3 = 0 or w2 3 = 1 ? w2 3 = 1), the count value of timer 2 is not initialized. ? timer 2 timer 2 has the watchdog timer function (wdt). when timer 2 is used as the wdt, note that the processing to initialize the count value and the execution of the wrst instruction. ? reading the count value stop the prescaler and then execute the tab1 instruction to read timer 1 data. ? writing to reload register r1 write the data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. ? notes when using the carrier wave output auto-control function ? execute the stcr instruction after setting the timer 1 and register c2 in order to start the carrier generating circuit operation. ? stop the timer 1 (w2 0 =0) after stopping the carrier generating circuit (spcr instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. ? if the carrier wave output auto-control function is invalidated (c2 0 =0) while the carrier wave output is auto-controlled, the output of port carr retains the state when the auto- control is invalidated regardless of timer 1 underflow. this state is released by timer 1 stop (w2 0 =0). when the carrier wave output auto-control function is validated (c2 0 =1) again after it is invalidated (c2 0 =0), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. however, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. ? use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto- control function is selected. if the orclk is used as the count source, a hazard may occur in port carr output because orclk is not synchronized with the carrier wave. ? when no carrier wave is selected with register c1 ((c1 3 c1 2 c1 1 c1 0 ) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function. ? d 5 /int pin when the interrupt valid waveform of d 5 /int pin is changed with the bit 2 of register i1 in software, be careful about the following notes. ? clear the bit 0 of register v1 to 0 and then change the interrupt valid waveform of d 5 /int pin with the bit 2 of register i1 (refer to figure 40 ). ? clear the bit 2 of register i1 to 0 and execute the snz0 instruction to clear the exf0 flag after executing at least one instruction (refer to figure 40 ). depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. la 4 ; ( 555 0 2 ) tv1a ; the snz0 instruction is valid la 4 ti1a ; change of the interrupt valid waveform nop snz0 ;the snz0 instruction is executed nop 5 : this bit is not related to the setting of int. . . . . . . one time prom version the operating power voltage of the one time prom version is within the range of 2.5 v to 5.5 v. multifunction note that the port d 5 output function can be used even when int function is selected. power down instruction (pof instruction, pof2 instruction) execute the pof or pof2 instruction immediately after executing the epof instruction to enter the power down state. note that system cannot enter the power down state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instrcution. program counter make sure that the pc h does not specify after the last page of the built-in rom. fig. 40 external 0 interrupt program example 12 11 list of precautions
4551 group users manual hardware 1-41 symbol the symbols shown below are used in the following list of instruction function and machine instructions. symbol a b dr e v1 v2 i1 w1 w2 w3 c1 c2 cr l1 l2 pu0 mr x y z dp pc pc h pc l sk sp cy r1 r2 rlc stck instk t1 t2 tlc t1f t2f contents register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) interrupt control register v1 (4 bits) general-purpose register v2 (4 bits) interrupt control register i1 (4 bits) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w3 (2 bits) carrier wave selection register c1 (4 bits) carrier wave output control register c2 (1 bit) carrier wave generating control flag lcd control regiser l1 lcd control register l2 pull-up control register pu0 (4 bits) clock control register mr (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits 5 8) stack pointer (3 bits) carry flag timer 1 reload register timer 2 reload register timer lc reload register system clock instruction clock timer 1 timer 2 timer lc timer 1 interrupt request flag timer 2 interrupt request flag contents watchdog timer flag interrupt enable flag external 0 interrupt request flag power down flag port d (8 bits) port p0 (4 bits) port p1 (4 bits) port p2 (4 bits) hexadecimal variable hexadecimal variable hexadecimal variable hexadecimal variable hexadecimal constant which represents the immediate value hexadecimal constant which represents the immediate value hexadecimal constant which represents the immediate value binary notation of hexadecimal variable a (same for others) direction of data movement data exchange between a register and memory decision of state shown before ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 5 p 4 p 3 p 2 p 1 p 0 hex. c + hex. number x (also same for others) symbol wdf inte exf0 p d p0 p1 p2 x y z p n i j a 3 a 2 a 1 a 0 ? ? ? ( ) m(dp) a p, a c + x note : the 4551 group just invalidates the next instruction when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does not change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. symbol
hardware 1-42 4551 group users manual function (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) + 1 (m(dp)) ? (a) (x) ? (x)exor(j) j = 0 to 15 (a) ? n n = 0 to 15 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (b) ? (rom(pc)) 7 to 4 (a) ? (rom(pc)) 3 to 0 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (a) ? (a) + (m(dp)) (a) ? (a) + (m(dp)) + (cy) (cy) ? carry (a) ? (a) + n n = 0 to 15 (a) ? (a)and(m(dp)) (a) ? (a)or(m(dp)) (cy) ? 1 (cy) ? 0 (cy) = 0 ? (a) ? (a) ? cy ? a 3 a 2 a 1 a 0 list of instruction function grouping grouping mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar mnemonic tab tba tay tya teab tabe tda tad taz tax tasp lxy x, y lz z iny dey tam j xam j xamd j function (a) ? (b) (b) ? (a) (a) ? (y) (y) ? (a) (e 7 Ce 4 ) ? (b) (e 3 Ce 0 ) ? (a) (b) ? (e 7 Ce 4 ) (a) ? (e 3 Ce 0 ) (dr 2 Cdr 0 ) ? (a 2 Ca 0 ) (a 2 Ca 0 ) ? (dr 2 Cdr 0 ) (a 3 ) ? 0 (a 1 , a 0 ) ? (z 1 , z 0 ) (a 3 , a 2 ) ? 0 (a) ? (x) (a 2 Ca 0 ) ? (sp 2 Csp 0 ) (a 3 ) ? 0 (x) ? x, x = 0 to 15 (y) ? y, y = 0 to 15 (z) ? z, z = 0 to 3 (y) ? (y) + 1 (y) ? (y) C 1 (a) ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) C 1 register to register transfer ram addresses ram to register transfer arithmetic operation ram to register transfer bit operation function (mj(dp)) ? 1 j = 0 to 3 (mj(dp)) ? 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? n = 0 to 15 (pc l ) ? a 6 Ca 0 (pc h ) ? p (pc l ) ? a 6 Ca 0 (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? 2 (pc l ) ? a 6 Ca 0 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? a 6 Ca 0 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 mnemonic sb j rb j szb j seam sea n b a bl p, a bla p bm a bml p, a bmla p rti rt rts grouping comparison operation branch operation subroutine operation return operation list of instruction function
4551 group users manual hardware 1-43 list of instruction function (continued) interrupt operation function (tlc) ? (a) (rlc) ? (a) (t1f) = 1 ? after skipping the next instruction, (t1f) ? 0 (t2f) = 1 ? after skipping the next instruction, (t2f) ? 0 (a) ? (p0) (p0) ? (a) (a) ? (p1) (p1) ? (a) (a) ? (p2) (d) ? 1 (d(y)) ? 0 (y) = 0 to 7 (d(y)) ? 1 (y) = 0 to 7 (pu0) ? (a) (a) ? (pu0) (l1) ? (a) (a) ? (l1) (l2) ? (a) mnemonic tlca snzt1 snzt2 iap0 op0a iap1 op1a iap2 cld rd sd tpu0a tapu0 tl1a tal1 tl2a timer operation timer operation input/output operation lcd control operation function (c1) ? (a) carrier wave generating start carrier wave generating stop (c2 0 ) ? (a 0 ) (pc) ? (pc) + 1 transition to clock operating mode transition to ram back-up mode power down instruction (pof, pof2) valid (p) = 1 ? (wdf) ? 0, (wef) ? 1 (a) ? (mr) (mr) ? (a) (a) ? (v2) (v2) ? (a) grouping mnemonic tc1a stcr spcr tc2a nop pof pof2 epof snzp wrst tamr tmra tav2 tv2a carrier wave generating operation other operation function (inte) ? 0 (inte) ? 1 (exf0) = 1 ? after skipping the next instruction, (exf0) ? 0 i1 2 = 1 : (int0) = h ? i1 2 = 0 : (int0) = l ? (a) ? (v1) (v1) ? (a) (a) ? (i1) (i1) ? (a) (a) ? (w1) (w1) ? (a) (a) ? (w2) (w2) ? (a) (a 1 , a 0 ) ? (w3 1 , w3 0 ) (w3 1 , w3 0 ) ? (a 1 , a 0 ) (b) ? (t1 7 Ct1 4 ) (a) ? (t1 3 Ct1 0 ) at timer 1 stop ( w2 0 =0) (r1 7 Cr1 4 ) ? (b) (t1 7 Ct1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) (t1 3 Ct1 0 ) ? (a) at timer 1 operating (w2 0 =1), (r1 7 Cr1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) mnemonic di ei snz0 snzi0 tav1 tv1a tai1 ti1a taw1 tw1a taw2 tw2a taw3 tw3a tab1 t1ab grouping grouping list of instruction function
hardware 1-44 4551 group users manual instruction code table instruction code table hex. notation d 9 Cd 4 000000 d 3 C d 0 000001 000100 000101000110 000111001000001001 001010 001011 001100 001101001110 001111 010000 010111 011000 011111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f nop C pof snzp di ei rc sc C am amc tya C tba C 00 bla cld C iny rd sd C dey and or teab C cma rar tab tay 01 szb 0 sean seam C C tda tabe C C C C szc 02 bmla C C C C C C C snz0 C C tv1a 03 C C C C rt rts rti C 04 tasp tad tax taz tav1 C C C C C epof lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 sb 0 sb 1 sb 2 sb 3 05 06 07 08 09 0a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 0b bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml 0c 0d bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl 0e 0f bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 10C17 b b b b b b b b b b b b b b b b 18C1f szb 1 szb 2 szb 3 the above table shows the relationship between machine language codes and machine language instructions. d 3 Cd 0 show the low-order 4 bits of the machine language code, and d 9 Cd 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked C. the codes for the second word of a two-word instruction are described below. * cannot be used at m34551m4. bl bml bla bmla sea the second word 1 0 p a a a a a a a 1 0 p a a a a a a a 1 0 p p 0 0 p p p p 1 0 p p 0 0 p p p p 0 0 0 1 1 1 n n n n snzi0 tv2a tav2 C C tabp 16 tabp 17 tabp 18 tabp 19 tabp 20 tabp 21 tabp 22 tabp 23 tabp 24 tabp 25 tabp 26 tabp 27 tabp 28 tabp 29 tabp 30 tabp 31 pof2 C tabp 32* tabp 48* tabp 33* tabp 49* tabp 34* tabp 50* tabp 35* tabp 51* tabp 36* tabp 52* tabp 37* tabp 53* tabp 38* tabp 54* tabp 39* tabp 55* tabp 40* tabp 56* tabp 41* tabp 57* tabp 42* tabp 58* tabp 43* tabp 59* tabp 44* tabp 60* tabp 45* tabp 61* tabp 46* tabp 62* tabp 47* tabp 63* bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl 000010 000011
4551 group users manual hardware 1-45 instruction code table (continued) instruction code table hex. notation d 9 ? 4 100000 d 3 d 0 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111 110000 111111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f tw1a tw2a 20 ti1a 21 op0a 22 23 24 tai1 taw1 taw2 25 26 27 28 29 2a iap0 iap1 snzt2 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 2b tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 2c xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 2d xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 2e 2f lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy 30?f op1a snzt1 wrst tma 0 tam 0 xam 0 xami 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 xamd 0 iap2 the above table shows the relationship between machine language codes and machine language instructions. d 3 ? 0 show the low-order 4 bits of the machine language code, and d 9 ? 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only th e first word of each instruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below. bl bml bla bmla sea the second word 1 0 p a a a a a a a 1 0 p a a a a a a a 1 0 p p 0 0 p p p p 1 0 p p 0 0 p p p p 0 0 0 1 1 1 n n n n tpu0a t1ab tab1 tmra tamr tapu0 tw3a tl1a tl2a tal1 tlca taw3 stcr tc1a spcr tc2a
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-46 machine instructions 4551 group users manual register to register transfer ram addresses machine instructions tab tba tay tya teab tabe tda tad taz tax tasp lxy x, y lz z iny dey 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 00010010z 1 z 0 0000010011 0000010111 (a) ? (b) (b) ? (a) (a) ? (y) (y) ? (a) (e 7 Ce 4 ) ? (b) (e 3 Ce 0 ) ? (a) (b) ? (e 7 Ce 4 ) (a) ? (e 3 Ce 0 ) (dr 2 Cdr 0 ) ? (a 2 Ca 0 ) (a 2 Ca 0 ) ? (dr 2 Cdr 0 ) (a 3 ) ? 0 (a 1 , a 0 ) ? (z 1 , z 0 ) (a 3 , a 2 ) ? 0 (a) ? (x) (a 2 Ca 0 ) ? (sp 2 Csp 0 ) (a 3 ) ? 0 (x) ? x, x = 0 to 15 (y) ? y, y = 0 to 15 (z) ? z, z = 0 to 3 (y) ? (y) + 1 (y) ? (y) C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 01e 00e 01f 00c 01a 02a 029 051 053 052 050 3xy 048 +z 013 017
skip condition detailed description carry flag cy 4551 group users manual hardware 1-47 machine instructions C C C C C C C C C C C C C C C C C C C C C C C C C C continuous description C (y) = 0 (y) = 15 transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of registers a and b to register e. transfers the contents of register e to registers a and b. transfers the contents of register a to register d. transfers the contents of register d to register a. transfers the contents of register z to register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-48 machine instructions 4551 group users manual ram to register transfer arithmetic operation tam j xam j xamd j xami j tma j la n tabp p (a) ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) C 1 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) + 1 (m(dp)) ? (a) (x) ? (x)exor(j) j = 0 to 15 (a) ? n n = 0 to 15 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (b) ? (rom(pc)) 7 to 4 (a) ? (rom(pc)) 3 to 0 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (note) 1 1 1 1 1 1 3 1 1 1 1 1 1 1 2c j 2d j 2f j 2e j 2b j 07 n 08 p +p 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 000111nnnn 0010p 5 p 4 p 3 p 2 p 1 p 0 note: p is 0 to 31 for m34551m4 and p is 0 to 63 for m34551m8 and m34551e8. machine instructions (continued)
skip condition detailed description carry flag cy 4551 group users manual hardware 1-49 machine instructions C C (y) = 15 (y) = 0 C continuous description C C C C C C C C after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. after transferring the contents of register a to m(dp), an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, 1 stage of stack register is used.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-50 machine instructions 4551 group users manual arithmetic operation bit operation comparison operation am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn 00a 00b 06n 018 019 007 006 02f 01c 01d 05 c +j 04 c +j 02 j 02 6 02 5 07 n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 (a) ? (a) + (m(dp)) (a) ? (a) + (m(dp))+ (cy) (cy) ? carry (a) ? (a) + n n = 0 to 15 (a) ? (a)and(m(dp)) (a) ? (a)or(m(dp)) (cy) ? 1 (cy) ? 0 (cy) = 0 ? (a) ? (a) ? cy ? a 3 a 2 a 1 a 0 (mj(dp)) ? 1 j = 0 to 3 (mj(dp)) ? 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? n = 0 to 15 machine instructions (continued)
skip condition detailed description carry flag cy 4551 group users manual hardware 1-51 machine instructions C C overflow = 0 C C C C (cy) = 0 C C C C (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n C 0/1 C C C 1 0 C C 0/1 C C C C C adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. performs the and operation between the contents of register a and the contents of m(dp), and stores the result in register a. performs the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets carry flag cy to 1. clears carry flag cy to 0. skips the next instruction when the contents of carry flag cy is 0. stores the ones complement for register as contents in register a. rotates the contents of register a including the contents of carry flag cy to the right by 1 bit. sets the contents of bit j (bit specified by the value j in the immediate field) of m(dp) to 1. clears the contents of bit j (bit specified by the value j in the immediate field) of m(dp) to 0. skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. skips the next instruction when the contents of register a is equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-52 machine instructions 4551 group users manual branch operation subroutine operation return operation b a bl p, a bla p bm a bml p, a bmla p rti rt rts 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 10p 5 p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 10p 5 p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 18 a +a 0e p +p 2p a +a 01 0 2p p 1a a 0c p +p 2pa +a 03 0 2p p 04 6 04 4 04 5 1 2 2 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 (pc l ) ? a 6 Ca 0 (pc h ) ? p (pc l ) ? a 6 Ca 0 (note) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (note) (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? 2 (pc l ) ? a 6 Ca 0 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? a 6 Ca 0 (note) (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (note) (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 note: p is 0 to 31 for m34551m4 and p is 0 to 63 for m34551m8 and m34551e8. machine instructions (continued)
skip condition detailed description carry flag cy 4551 group users manual hardware 1-53 machine instructions C C C C C C C C skip unconditionally C C C C C C C C C branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-54 machine instructions 4551 group users manual interrupt operation machine instructions (continued) di ei snz0 snzi0 tav1 tv1a tai1 ti1a snzt1 snzt2 taw1 tw1a taw2 tw2a taw3 tw3a 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 1001010011 1000010111 1010000000 1010000001 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 00 4 00 5 03 8 03 a 054 03f 253 217 280 281 24b 20e 24c 20f 24d 210 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (inte) ? 0 (inte) ? 1 (exf0) = 1 ? after skipping the next instruction, (exf0) ? 0 i1 2 = 1 : (int) = h ? i1 2 = 0 : (int) = l ? (a) ? (v1) (v1) ? (a) (a) ? (i1) (i1) ? (a) (t1f) = 1 ? after skipping the next instruction (t1f) ? 0 (t2f) = 1 ? after skipping the next instruction (t2f) ? 0 (a) ? (w1) (w1) ? (a) (a) ? (w2) (w2) ? (a) (a 1 , a 0 ) ? (w3 1 , w3 0 ) (w3 1 , w3 0 ) ? (a 1 , a 0 ) timer operation
skip condition detailed description carry flag cy 4551 group users manual hardware 1-55 machine instructions C C (exf0) = 1 (int) = h however, i1 2 = 1 (int) = l however, i1 2 = 0 C C C C (t1f) = 1 (t2f) =1 C C C C C C C C C C C C C C C C C C C C C C C clears the interrupt enable flag inte to 0, and disables the interrupt. sets the interrupt enable flag inte to 1, and enables the interrupt. skips the next instruction when the contents of exf0 flag is 1. after skipping, clears the exf0 flag to 0. when bit 2 (i1 2 ) of register i1 is 1 : skips the next instruction when the level of int pin is h. when bit 2 (i1 2 ) of register i1 is 0 : skips the next instruction when the level of int pin is l. transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. skips the next instruction when the contents of t1f flag is 1. after skipping, clears t1f flag. skips the next instruction when the contents of t2f flag is 1. after skipping, clears t2f flag. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w3 to register a. transfers the contents of register a to timer control register w3.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-56 machine instructions 4551 group users manual tab1 t1ab tlca iap0 op0a iap1 op1a iap2 cld rd sd tpu0a tapu0 timer operation 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1001110000 1000110000 1000001101 1001100000 1000100000 1001100001 1000100001 1001100010 0000010001 0000010100 0000010101 1000101101 1001010111 270 230 20d 260 220 261 221 262 011 014 015 22d 257 (b) ? (t1 7 Ct1 4 ) (a) ? (t1 3 Ct1 0 ) at timer 1 stop (w2 0 =0), (r1 7 Cr1 4 ) ? (b) (t1 7 Ct1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) (t1 3 Ct1 0 ) ? (a) at timer 1 operating (w2 0 =1), (r1 7 Cr1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) (tlc) ? (a) (rlc) ? (a) (a) ? (p0) (p0) ? (a) (a) ? (p1) (p1) ? (a) (a) ? (p2) (d) ? 1 (d(y)) ? 0 (y) = 0 to 7 (d(y)) ? 1 (y) = 0 to 7 (pu0) ? (a) (a) ? (pu0) machine instructions (continued) input/output operation
skip condition detailed description carry flag cy 4551 group users manual hardware 1-57 machine instructions C C C C C C C C C C C C C C C C C C C C C C C C C C transfers the contents of timer 1 to registers a and b. when stopping (w2 0 =0), transfers the contents of registers a and b to timer 1 and timer 1 reload register. when operating (w2 0 =1), transfers the contents of registers a and b only to timer 1 reload register. transfers the contents of register a to timer lc and timer lc reload register. transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to register a. sets port d to 1. clears a bit of port d specified by register y to 0. sets a bit of port d specified by register y to 1. transfers the contents of register a to pull-up control register pu0. transfers the contents of pull-up control register pu0 to register a.
function mnemonic d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation type of instructions parameter number of words number of cycles instruction code hardware 1-58 machine instructions 4551 group users manual tl1a tal1 tl2a tc1a stcr spcr tc2a nop pof pof2 epof snzp wrst tamr tmra tav2 tv2a 1000001010 1001001010 1000001011 1010101000 1010011000 1010011001 1010101001 0000000000 0000000010 0000001000 0001011011 0000000011 1010100000 1001010010 1000010110 0001010101 0000111110 20a 24a 20b 2a8 298 299 2a9 000 002 008 05b 003 2a0 252 216 055 03e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (l1) ? (a) (a) ? (l1) (l2) ? (a) (c1) ? (a) carrier wave generating start carrier wave generating stop (c2 0 ) ? (a 0 ) (pc) ? (pc) + 1 transition to clock operating mode transition to ram back-up mode power down instruction (pof, pof2) valid (p) = 1 ? (wdf) ? 0, (wef) ? 1 (a) ? (mr) (mr) ? (a) (a) ? (v2) (v2) ? (a) machine instructions (continued) lcd control operation other operation carrier generating circuit operation
skip condition detailed description carry flag cy 4551 group users manual hardware 1-59 machine instructions C C C C C C C C C C C (p) = 1 C C C C C C C C C C C C C C C C C C C C C C transfers the contents of register a to lcd control register l1. transfers the contents of register l1 to register a. transfers the contents of register a to lcd control register l2. transfers the contents of register a to carrier wave selection register c1. starts generating carrier wave. stops generating carrier wave. transfers the contents of register a to carrier wave output control register c2. no operation puts the system in clock operating mode state by executing the pof instruction after executing the epof instruction. f(x cin ) oscillation, lcd, timer lc and timer 2 are operated. puts the system in ram back-up mode state by executing the pof2 instruction after executing the epof instruction. oscillation is stopped. validates the power down instruction (pof, pof2) which is executed after the epof instruction by executing the epof instruction. skips the next instruction when p flag is 1. after skipping, p flag remains unchanged. operates the watchdog timer and initializes the watchdog timer flag (wdf). transfers the contents of clock control register mr to register a. transfers the contents of register a to clock control register mr. transfers the contents of general-purpose register v2 to register a. transfers the contents of register a to general-purpose register v2.
hardware 1-60 4551 group users manual control registers v1 3 v1 2 v1 1 v1 0 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit 0 1 0 1 0 1 0 1 interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w prescaler control bit prescaler dividing ratio selection bit timer 1 count source selection bits timer control register w1 w1 3 w1 2 w1 1 w1 0 at reset : 0000 2 at power down : 0000 2 0 1 0 1 r/w stop (prescaler state initialized) operating instruction clock (instck) divided by 4 instruction clock (instck) divided by 8 count source prescaler output (orclk) carrier output (carry) carrier output divided by 2 (carry/2) w1 1 0 0 1 1 w1 0 0 1 0 1 timer control register w2 at reset : 1000 2 at power down : C C C 0 2 r/w 0 1 f(x cin ) prescaler output (orclk) w2 3 w2 2 w2 1 w2 0 timer 2 count source selection bit timer 2 count value selection bits timer 1 control bit w2 2 0 0 1 1 w2 1 0 1 0 1 count source underflow occur every 2 14 count underflow occur every 2 13 count not available not available stop (timer 1 state retained) operating 0 1 timer control register w3 at reset : 00 2 at power down : state retained r/w 0 1 0 1 bit 3 of timer 2 is output (timer 2 count source divided by 16) system clock (stck) stop (timer lc state retained) operating w3 1 w3 0 timer lc count source selection bit timer lc control bit note: r represents read enabled, and w represents write enabled. C represents state retained. control registers
4551 group users manual hardware 1-61 control registers (continued) i1 3 i1 2 i1 1 i1 0 not used interrupt valid waveform for int pin selection bit (note 2) not used not used 0 1 0 1 0 1 0 1 this bit has no function, but read/write is enabled. falling waveform (l level of int pin is recognized with the snzi0 instruction) rising waveform (h level of int pin is recognized with the snzi0 instruction) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. interrupt control register i1 r/w at reset : 0000 2 at power down : state retained pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 0000 2 at power down : state retained pull-up control register pu0 r/w pu0 3 pu0 2 pu0 1 pu0 0 system clock (stck) selection bit f(x cin ) oscillation circuit control bit f(x in ) oscillation circuit control bit clock selection bit at reset : 1000 2 at power down : state retained clock control register mr r/w mr 3 mr 2 mr 1 mr 0 mr 0 =0 f(x in ) mr 0 =1 f(x cin ) mr 0 =0 f(x in )/4 mr 0 =1 f(x cin )/4 f(x cin ) oscillation stop, ports d 6 and d 7 selected f(x cin ) oscillation enabled, ports d 6 and d 7 not selected oscillation enabled oscillation stop f(x in ) f(x cin ) 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: depending on the input state of d 5 /int pin, the external interrupt request flag exf0 may be set to 1 when the contents of i1 2 is changed. accordingly, set a value to bit 2 of register i1 and execute the snz0 instruction to clear the exf0 flag after executing at least one instruction. control registers
hardware 1-62 4551 group users manual c1 3 c1 2 c1 1 c1 0 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 control registers (continued) at reset : 0111 2 at power down : 0111 2 carrier wave selection register c1 w carrier wave frequency stck/24 stck/24 stck/16 stck/16 stck/2 no carrier wave not available l fixed stck/12 stck/12 stck/8 stck/8 stck no carrier wave not available l fixed duty 1/3 1/2 1/4 1/2 1/2 1/3 1/2 1/4 1/2 1/2 carrier wave selection bits c2 0 auto-control output by timer 1 is invalid auto-control output by timer 1 is valid carrier wave output auto-control bit 0 1 at reset : 0 2 carrier wave output control register c2 at power down : 0 2 w cr carrier wave generating stop (spcr instruction) carrier wave generating start (stcr instruction) carrier wave generating control 0 1 at reset : 0 2 carrier wave generating control flag cr at power down : 0 2 w note: w represents write enabled. control registers
4551 group users manual hardware 1-63 control registers (continued) not used lcd on/off bit lcd duty and bias selection bits lcd control register l1 l1 3 l1 2 l1 1 l1 0 at reset : 0000 2 at power down : state retained 0 1 0 1 r/w this bit has no function, but read/write is enabled off on not available l1 1 0 0 1 1 l1 0 0 1 0 1 duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 lcd control register l2 at reset : 1111 2 at power down : state retained w 0 1 0 1 0 1 0 1 seg 19 p2 3 seg 18 p2 2 seg 17 p2 1 seg 16 p2 0 l2 3 l2 2 l2 1 l2 0 p2 3 /seg 19 pin function switch bit p2 2 /seg 18 pin function switch bit p2 1 /seg 17 pin function switch bit p2 0 /seg 16 pin function switch bit 4-bit general-purpose register. the data transfer between register a and this register is performed with the tv2a and tav2 instructions. at reset : 0000 2 general-purpose register v2 at power down : 0000 2 r/w note: r represents read enabled, and w represents write enabled. control registers
hardware 1-64 4551 group users manual product m34551e8-xxxfp m34551e8fp prom size ( 5 10 bits) 8192 words ram size ( 5 4 bits) 280 words package 48p6s-a rom type one time prom [shipped after writing] (shipped after writing and test in factory) one time prom [shipped in blank] pin configuration (top view) built-in prom version in addition to the mask rom version, the 4551 group has the programmable rom version software compatible with mask rom. the one time prom version has prom which can only be written to and not be erased. the built-in prom version has functions similar to those of the mask rom version, but it has a prom mode that enables writing to built-in prom. table 19 shows the product of built-in prom version. figure 41 shows the pin configurations of built-in prom version. the one time prom version has pin-compatibility with the mask rom version. table 19 product of built-in prom version outline 48p6s-a fig. 41 pin configuration of built-in prom version built-in prom version 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 com 2 com 3 seg 0 seg 1 m34551e8-xxxfp seg 11 seg 14 seg 15 seg 9 v ss x out x in p1 0 p1 1 p1 2 p1 3 d 1 d 2 d 3 d 4 p0 0 p0 1 p0 2 p0 3 d 0 reset d 7 /x cout d 6 /x cin carr v dd cnv ss v ss d 5 / int com 1 com 0 seg 10 seg 13 seg 12 p2 3 / seg 19 p2 2 / seg 18 p2 0 / seg 16 p2 1 / seg 17
4551 group users manual hardware 1-65 fig. 42 prom memory map fig. 43 flow of writing and test of the product shipped in blank (1) prom mode the built-in prom version has a prom mode in addition to a normal operation mode. the prom mode is used to write to and read from the built-in prom. in the prom mode, the programming adapter can be used with a general-purpose prom programmer to write to or read from the built-in prom as if it were m5m27c256k. programming adapter is listed in table 20. contact addresses at the end of this book for the appropriate prom programmer. ? writing and reading of built-in prom programming voltage is 12.5 v. write the program in the prom of the built-in prom version as shown in figure 42. (2) notes on handling a high-voltage is used for writing. take care that overvoltage is not applied. take care especially at turning on the power. for the one time prom version shipped in blank, mitsubishi electric corp. does not perform prom writing test and screening in the assembly process and following processes. in order to improve reliability after writing, performing writing and test according to the flow shown in figure 43 before using is recommended. ( products shipped in blank: prom contents is not written in factory when shipped) table 20 programming adapter microcomputer m34551e8-xxxfp, m34551e8fp programming adapter pca7414 writing with prom programmer screening (leave at 150 ? for 40 hours) (note) verify test with prom programmer function test in target device since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 ? exceeding 100 hours. note: address 0000 16 1fff 16 4000 16 5fff 16 7fff 16 aaaaaaaaa a aaaaaaa a aaaaaaaaa 1 11 d 4 d 3 d 2 d 1 d 0 high-order 5 bits aaaaaaaaa aaaaaaaaa 1 11 d 4 d 3 d 2 d 1 d 0 low-order 5 bits set ff 16 to the shaded area. built-in prom version
hardware 1-66 4551 group users manual built-in prom version memo
chapter 2 chapter 2 application 2.1 i/o pins 2.2 interrupts 2.3 timers 2.4 carrier generating circuit 2.5 liquid crystal display 2.6 power down function 2.7 reset 2.8 oscillation circuit
2-2 application 2.1 i/o pins 4551 group users manual 2.1 i/o pins the 4551 group has the eight i/o pins, four input pins and eight output pins. (ports p2 0 Cp2 3 , d 5 Cd 7 are also used as segment output pins seg 16 Cseg 19 , int input pin, x cin , and x cout , respectively). this section describes each port i/o function, related registers, application example using each port function and notes. 2.1.1 i/o ports (1) port p0 port p0 is a 4-bit i/o port. port p0 has the key-on wakeup function and pull-up transistor. n input/output of port p0 l l data input to port p0 set the output latch of specified port p0i (i=0 to 3) to 1 with the op0a instruction. if the output latch is set to 0, l level can be input. the state of port p0 is transferred to register a when the iap0 instruction is executed. data output from port p0 the contents of register a is output to port p0 with the op0a instruction. the output structure is an n-channel open-drain (built-in pull-up resistor). (2) port p1 port p1 is a 4-bit i/o port. port p1 has the key-on wakeup function and pull-up transistor which turn on/off by setting register pu0. n input/output of port p1 l data input to port p1 set the output latch of specified port p1i (i=0 to 3) to 1 with the op1a instruction. if the output latch is set to 0, l level can be input. the state of port p1 is transferred to register a when the iap1 instruction is executed. data output from port p1 the contents of register a is output to port p1 with the op1a instruction. the output structure is an n-channel open-drain. note: when the pull-up function becomes valid, simultaneously, the key-on wakeup function becomes valid. accordingly, be careful when using the key-on wakeup function. (refer to the table 2.1.1 and notes for the power down function.) l
4551 group users manual application 2-3 2.1 i/o pins (3) port p2 port p2 is a 4-bit input port. n input of port p2 port p2 is also used as seg 16 Cseg 19 . accordingly, when ports p2 0 /seg 16 Cp2 3 /seg 19 are used as port p2, set the corresponding bits of the lcd control register l2 to 1. l data input to port p2 the state of port p2 is transferred to register a when the iap2 instruction is executed. (4) port d d 0 Cd 7 are eight independent output ports. n output of port d each pin of port d has an independent 1-bit wide output function. for output of ports d 0 Cd 7 , select one of port d with the register y of the data pointer first. l data output from port d set the output level to the output latch with the sd and rd instructions. the state of pin enters the high-impedance state when the sd instruction is executed. the states of all port d enter the high-impedance state when the cld instruction is executed. the state of pin becomes l level when the rd instruction is executed. the output structure is an n-channel open-drain. notes 1: when the sd and rd instructions are used, do not set 1000 2 or more to register y. 2: port d 6 is also used as x cin , and port d 7 is also used as x cout . accordingly, when using port d 6 and d 7 functions, set the clock control register mr 2 to 0.
2-4 application 2.1 i/o pins 4551 group users manual 2.1.2 related registers (1) pull-up control register pu0 register pu0 controls the on/off of the port p1 0 Cp1 3 pull-up transistor and the on/off of the key- on wakeup function. set the contents of this register through register a with the tpu0a instruction. the contents of register pu0 is transferred to register a with the tapu0 instruction. table 2.1.1 shows the pull-up control register pu0. table 2.1.1 pull-up control register pu0 pull-up control register pu0 at reset : 0000 2 at power down : state retained r/w pull-up transistor off, no key-on wakeup function pull-up transistor on, key-on wakeup function pull-up transistor off, no key-on wakeup function pull-up transistor on, key-on wakeup function pull-up transistor off, no key-on wakeup function pull-up transistor on, key-on wakeup function pull-up transistor off, no key-on wakeup function pull-up transistor on, key-on wakeup function port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu0 3 pu0 2 pu0 1 pu0 0 note: r represents read enabled, w represents write enabled. (2) lcd control register l2 register l2 is used to select the port p2 function or segment output pin function. set the contents of this register through register a with the tl2a instruction. table 2.1.2 shows the lcd control register l2. table 2.1.2 lcd control register l2 lcd control register l2 at reset : 1111 2 at power down : state retained w seg 19 p2 3 seg 18 p2 2 seg 17 p2 1 seg 16 p2 0 p2 3 /seg 19 function switch bit p2 2 /seg 18 function switch bit p2 1 /seg 17 function switch bit p2 0 /seg 16 function switch bit 0 1 0 1 0 1 0 1 note: w represents write enabled. l2 3 l2 2 l2 1 l2 0
4551 group users manual application 2-5 2.1 i/o pins (3) clock control register mr the oscillation circuit control bit is assigned to the bit 2 of the clock control register mr. set the contents of this register through register a with the tmra instruction. the contents of register mr is transferred to register a with the tamr instruction. table 2.1.3 shows the clock control register mr. table 2.1.3 clock control register mr clock control register mr at reset : 1000 2 at power down : state retained r/w mr 0 = 0 f(x in ) mr 0 = 1 f(x cin ) mr 0 = 0 f(x in )/4 mr 0 = 1 f(x cin )/4 (x cin ) oscillation stop, ports d 6 , d 7 selected (x cin ) oscillation enabled, ports d 6 , d 7 not selected oscillation enabled oscillation stop f(x in ) f(x cin ) system clock (stck) selection bit f(x cin ) oscillation circuit control bit f(x in ) oscillation circuit control bit clock selection bit 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when setting ports, mr 3 , mr 1 , mr 0 are not used. 3: do not stop the oscillation circuit selected with the clock selection bit (mr 0 ). note the stop of the oscillation circuit selected with the clock selection bit (mr 0 ) if the following setting is performed. example 1: (mr 3 mr 2 mr 1 mr 0 ) = 5 0 5 1 (f(x cin ) selected, f(x cin ) oscillation stop) example 2: (mr 3 mr 2 mr 1 mr 0 ) = 55 10 (f(x in ) selected, f(x in ) oscillation stop) 5 : 0 or 1. mr 3 mr 2 mr 1 mr 0
2-6 application 2.1 i/o pins 4551 group users manual 2.1.3 port application examples (1) key input by key scan key matrix can be set up by connecting keys externally because port d output structure is an n- channel open-drain and port p0 has the pull-up resistor. outline: the connecting required external part is just keys. specifications: port d is used to output l level and port p0 is used to input 16 keys. multiple key inputs are not detected. figure 2.1.1 shows the key input and figure 2.1.2 shows the key input timing. fig. 2.1.1 key input by key scan sw4 sw3 sw2 sw8 sw7 sw6 sw9 sw11 sw10 sw12 sw16 sw15 sw14 sw13 d 0 d 1 d 2 d 3 p0 0 p0 1 p0 2 p0 3 sw1 sw5 m34551
4551 group users manual application 2-7 2.1 i/o pins fig. 2.1.2 input timing of key scan high low d 0 high low high low high low d 1 d 2 d 3 iap0 iap0 iap0 iap0 input of sw13?w16 iap0 switch of key input selection port (d 0 ? d 1 ) waiting time for stabilizing until input reading of port (key input) key input cycle input of sw1?w4 input of sw9?w12 input of sw5?w8 input of sw1?w4 note: output from port d is high-impedance state.
2-8 application 2.1 i/o pins 4551 group users manual 2.1.4 notes on use (1) note when an i/o port is used as an input port set the output latch to 1 and input the port value before input. if the output latch is set to 0, l level can be input. (2) noise and latch-up prevention connect an approximate 0.1 m f bypass capacitor directly to the v ss line and the v dd line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. the cnv ss pin is also used as the v pp pin (programming voltage = 12.5 v) at the one time prom version. connect the cnv ss /v pp pin to v ss through an approximate 5 k w resistor which is connected to the cnv ss /v pp pin at the shortest distance. (3) note on multifunction port d 5 is also used as the int pin. note that the port d 5 output function can be used even when int pin function is selected. (4) connection of unused pins table 2.1.4 shows the connections of unused pins. (5) sd, rd instructions when the sd and rd instructions are used, do not set 1000 2 or more to register y. table 2.1.4 connections of unused pins pin d 0 Cd 4 , d 5 /int d 6 /x cin , d 7 /x cout p2 0 /seg 16 Cp2 3 /seg 19 carr seg 0 Cseg 15 com 0 Ccom 3 p0 0 Cp0 3 p1 0 Cp1 3 connection connect to v ss pin, or set the output latch to 0. select d 6 and d 7 and connect to v ss , or set the output latch to 0 and open. select p2 and connect to v ss , or select segment output function and open. open. open. open. set the output latch to 1 and open. open or connect to v ss (note). note: in order to connect ports p1 0 Cp1 3 to v ss , turn off their pull-up transistors (pull-up control register pu0i=0) by software. in order to make these pins open, turn on their pull-up transistors (register pu0i=1) by software, or turn off their pull-up transistors (register pu0i=0) and set the output latch to 0 (i = 0, 1, 2, or 3). be sure to select the key-on wakeup function and the pull-up function with every one port. (note in order to set the output latch to 0 and make pins open) ? after system is released from reset, a port is in a high-impedance state until the output latch of the port is set to 0 by software. accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. ? to set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (note in order to connect unused pins to v ss or v dd ) ? to avoid noise, connect the unused pins to v ss or v dd at the shortest distance using a thick wire.
application 2.2 interrupts 2-9 4551 group users manual 2.2 interrupts the 4551 group has three interrupt sources : external interrupt (int), timer 1 interrupt and timer 2 interrupt. this section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 interrupt functions (1) external interrupt (int) the interrupt request occurs by the change of input level of int pin. the interrupt valid waveform can be selected by the bit 2 of the interrupt control register i1. n external interrupt processing l when the interrupt is used the interrupt occurrence is enabled when the bit 0 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the external interrupt occurs, the interrupt processing is executed from address 0 in page 1. l when the interrupt is not used the interrupt is disabled and the snz0 instruction is valid when the bit 0 of register v1 is set to 0. (2) timer 1 interrupt the interrupt request occurs by the timer 1 underflow. n timer 1 interrupt processing l when the interrupt is used the interrupt occurrence is enabled when the bit 2 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. l when the interrupt is not used the interrupt is disabled and the snzt1 instruction is valid when the bit 2 of register v1 is set to 0. (3) timer 2 interrupt the interrupt request occurs by the timer 2 underflow. n timer 2 interrupt processing l when the interrupt is used the interrupt occurrence is enabled when the bit 3 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. l when the interrupt is not used the interrupt is disabled and the snzt2 instruction is valid when the bit 3 of register v1 is set to 0.
application 2.2 interrupts 2-10 4551 group users manual 2.2.2 related registers (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every interrupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. note: the interrupt enabled with the ei instruction is performed after the ei instruction and one more instruction. (2) interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register v1. set the contents of this register through register a with the tv1a instruction. in addition, the tav1 instruction can be used to transfer the contents of register v1 to register a. table 2.2.1 shows the interrupt control register v1. table 2.2.1 interrupt control register v1 interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w interrupt disabled ( snzt2 instruction is valid) interrupt enabled ( snzt2 instruction is invalid) interrupt disabled ( snzt1 instruction is valid) interrupt enabled ( snzt1 instruction is invalid) this bit has no function, but read/write is enabled. interrupt disabled ( snz0 instruction is valid) interrupt enabled ( snz0 instruction is invalid) timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit v1 3 v1 2 v1 1 v1 0 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. (3) interrupt request flag the activated condition for each interrupt is examined. each interrupt request flag is set to 1 when the activated condition is satisfied, even if the interrupt is disabled by the inte flag or its interrupt enable bit. each interrupt request flag is cleared to 0 when either; ?an interrupt occurs, or ?the next instruction is skipped with a skip instruction.
application 2.2 interrupts 2-11 4551 group users manual (4) interrupt control register i1 the interrupt valid waveform for int pin is assigned to the bit 2 of register i1. set the contents of this register through register a with the ti1a instruction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. table 2.2.2 shows the interrupt control register i1. table 2.2.2 interrupt control register i1 interrupt control register i1 at reset : 0000 2 at power down : state retained r/w this bit has no function, but read/write is enabled. falling waveform (l level of int pin is recognized with the snzi0 instruction) rising waveform (h level of int pin is recognized with the snzi0 instruction) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. not used interrupt valid waveform for int pin selection bit( note 2 ) not used not used 0 1 0 1 0 1 0 1 i1 3 i1 2 i1 1 i1 0 notes 1: r represents read enabled, and w represents write enabled. 2: depending on the input state of d 5 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. accordingly, set a value to the bit 2 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction.
application 2.2 interrupts 2-12 4551 group users manual 2.2.3 interrupt application examples (1) external interrupt the int pin is used for external interrupts, of which valid waveforms can be chosen, which can recognize the change of both edges (h ? l or l ? h). outline: an external interrupt can be used by dealing with the change of edge (h ? l or l ? h) in both directions as a trigger. specifications: an interrupt occurs by the change of an external signals edge (h ? l or l ? h). figure 2.2.1 shows an operation example of an external interrupt, and figure 2.2.2 shows a setting example of an external interrupt. (2) timer 1 interrupt constant period interrupts by a setting value to timer 1 can be used. outline: the constant period interrupts by the timer 1 underflow signal can be used. specifications: prescaler and timer 1 divide the system clock frequency f(x in ) = 3.6 mhz, and the timer 1 interrupt occurs every 1 ms. figure 2.2.3 shows a setting example of the timer 1 constant period interrupt. (3) timer 2 interrupt timer 2 is the fixed dividing frequency, and the constant period interrupts which the count source is divided by 2 13 or 2 14 can be used. outline: the constant period interrupts by the timer 2 underflow signal can be used. specifications: timer 2 divides the sub-clock frequency f(x cin ) = 32.768 khz, and the timer 2 interrupt occurs every 0.5 sec. figure 2.2.4 shows a setting example of the timer 2 constant period interrupt. fig. 2.2.1 external interrupt operation example d 5 /int i1 2 int valid waveform falling rising falling rising falling rising ? ? ? ? setting of valid waveform by i1 2 d 5 /int ? ? ? ? interrupt occurs after setting the valid waveform to ?alling.? the valid waveform of the next interrupt is set to ?ising. when the interrupt which valid waveform is set to ?ising?occurs, the opposite of the above processing is performed.
application 2.2 interrupts 2-13 4551 group users manual fig. 2.2.2 external interrupt setting example note: the valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. set port port used for external interrupt is set to input port. set to input ( sd instruction) clear the external interrupt activated condition ( snz0 instruction) 555 0 b3 b0 b3 b0 5 1 55 b0 b3 5 0 55 interrupt enable flag inte interrupt control register v1 ? disable interrupts external interrupt is temporarily disabled. all interrupts disabled ( di instruction) external interrupt occur disabled ( tv1a instruction) port d 5 output latch ? a set valid waveform valid waveform of int pin is selected. interrupt control register i1 interrupt control register i1 rising waveform selected ( ti1a instruction) falling waveform selected ( ti1a instruction) h note when interrupt valid waveform is changed when a is executed, depending on the input state of int pin, the interrupt request flag exf0 may be set to ?. accordingly, insert the nop instruction after the ti1a instruction. ? clear interrupt request external interrupt activated condition is cleared. external interrupt request flag exf0 ? h note when interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag exf0, insert the nop instruction after the snz0 instruction. ? enable interrupts external interrupt which is temporarily disabled is enabled. interrupt control register v1 interrupt enable flag inte external interrupt occur enabled ( tv1a instruction) all interrupts enabled ( ei instruction) b3 b0 555 1 ? external interrupt execution started 5 ?: it can be ??or ?.
application 2.2 interrupts 2-14 4551 group users manual fig. 2.2.3 timer 1 constant period interrupt setting example 1ms = (3.6 mhz) 5 4 5 3 5 4 5 (74 + 1) b3 b0 5 0 55 b3 b0 0 b3 b0 555 1 b3 b0 1 b3 b0 5 0 5 5 0 0 1 C 1 interrupt enable flag inte interrupt control register v1 disable interrupts timer 1 interrupt is temporarily disabled. a set timer value timer 1 count time is set. (the formula is shown ] a below.) ? clear interrupt request the timer 1 interrupt activated condition is cleared. timer 1 interrupt request flag t1f h note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t1f, insert the nop instruction after the snzt1 instruction. ? enable interrupts the timer 1 interrupt which is temporarily disabled is enabled. interrupt control register v1 interrupt enable flag inte constant period interrupt execution started 5 : it can be 0 or 1. 0 all interrupts disabled ( di instruction) timer 1 interrupt occur disabled ( tv1a instruction) clear the timer 1 interrupt activated condition ( snzt1 instruction) 0 timer 1 interrupt occur enabled ( tv1a instruction) all interrupts enabled ( ei instruction) timer control register v1 stop timer operation timer 1 operation is temporarily stopped. timer 1 operation stop ( tw2a instruction) 4a 16 prescaler divided by 4 selected ( tw1a instruction) timer count value 74 set ( t1ab instruction) ? start timer 1 operation the timer 1 operation which is temporarily stopped is restarted. timer control register w2 timer 1operation start ( tw2a instruction) system clock instruction clock prescaler dividing ratio timer 1 count value ] a the prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1ms are set as follows: 5 55 1 timer control register w1 timer 1 reload register r1
application 2.2 interrupts 2-15 4551 group users manual fig. 2.2.4 timer 2 constant period interrupt setting example 0.5s = (32.768khz) 5 2 b3 b0 0 b3 b0 0 1 b3 b0 00 g0 h ? enable interrupts the timer 2 interrupt which is temporarily disabled is enabled. interrupt control register v1 interrupt enable flag inte interrupt enable flag inte interrupt control register v1 disable interrupts timer 2 interrupt is temporarily disabled. ? all interrupts disabled ( di instruction) timer 1 interrupt occur disabled ( tv1a instruction) 555 set timer value timer 2 count time is set. (only when timer count value is 2 or 2 , the formula is shown ] a below.) timer count value 2 set ( tw2a instruction) timer count value 2 set ( tw2a instruction) when timer count value = 2 , timer control register w2 when timer count value = 2 , timer control registerw2 13 14 13 14 55 55 13 14 a reset timer value and set count source timer 2 counter is initialized. (initialization is performed only by setting w2 3 from 0 to 1.) timer control register w2 this processing and setting timer value shown can be executed simultaneously. timer control register w2 timer control register w2 b3 b0 0 b3 b0 1 b3 b0 0 555 555 555 timer 2 reset timer 2 count source is returned to x cin . ( tw2a instruction) ? clear interrupt request the timer 2 interrupt activated condition is cleared. timer 2 interrupt request flag t2f clear the timer 2 interrupt activated condition ( snzt2 instruction) ? h note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t2f, insert the nop instruction after the snzt2 instruction. timer 2 interrupt occur enabled ( tv1a instruction) all interrupts enabled ( ei instruction) ? b3 b0 1 555 constant period interrupt execution started 5 ?: it can be ??or ?. sub-clock ] a the timer 2 count value to make the interrupt occur every 0.5s is set as follows: timer 2 count value 14 ?
application 2.2 interrupts 2-16 4551 group users manual 2.2.4 notes on use (1) setting of external interrupt valid waveform depending on the input state of d 5 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. accordingly, set a value to the bit 2 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction. (2) multiple interrupts multiple interrupts cannot be used in the 4551 group. (3) notes on interrupt processing when the interrupt occurs, at the same time, the interrupt enable flag inte is cleared to 0 (interrupt disable state). in order to enable the interrupt at the same time when system returns from the interrupt, write ei and rti instructions continuously. (4) d 5 /int pin the d 5 /int pin need not be selected the external interrupt input int function or the normal output port d 5 function. however, the exf0 flag is set to 1 when a valid waveform output from port d 5 is input to int pin even if it is used as an output port d 5 . (5) power down instruction be sure to disable interrupts by executing the di instruction before executing the epof instruction.
application 2.3 timers 2-17 4551 group users manual 2.3 timers the 4551 group has an 8-bit timer with a reload register, a 4-bit timer and the 14-bit fixed dividing frequency timer which has the watchdog timer function. this section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 timer functions (1) timer 1 n timer operation n carrier wave output auto-control function (refer to section 2.4 carrier generating circuit for details.) (2) timer 2 n timer operation (timer 2 has the function to return from clock operation mode ( pof instruction execution)) n watchdog function watchdog timer provides a method to reset the system when a program runs wild. when the wrst instruction is executed after system is released from reset, in this time, the watchdog timer starts operating. system reset is performed if the wrst instruction is not performed while timer 2 counts 2 13 . (3) timer lc n lcd frame clock generating 2.3.2 related registers (1) interrupt control register v1 the timer 1 interrupt enable bit is assigned to the bit 2, and the timer 2 interrupt enable bit is assigned to the bit 3. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. table 2.3.1 shows the interrupt control register v1. table 2.3.1 interrupt control register v1 interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w interrupt disabled ( snzt2 instruction is valid) interrupt enabled ( snzt2 instruction is invalid) interrupt disabled ( snzt1 instruction is valid) interrupt enabled ( snzt1 instruction is invalid) this bit has no function, but read/write is enabled. interrupt disabled ( snz0 instruction is valid) interrupt enabled ( snz0 instruction is invalid) timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit v1 3 v1 2 v1 1 v1 0 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when timer is used, v1 0 is not used.
application 2.3 timers 2-18 4551 group users manual (2) timer control register w1 the timer 1 count source selection bits are assigned to bits 0 and 1, and the prescaler dividing ratio selection bit is assigned to the bit 2, and the prescaler control bit is assigned to the bit 3. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. table 2.3.2 shows the timer control register w1. table 2.3.2 timer control register w1 timer control register w1 at reset : 0000 2 at power down : 0000 2 r/w stop (prescaler state initialized) operating instruction clock (instck) divided by 4 instruction clock (instck) divided by 8 count source prescaler output (orclk) carrier output (carry) carrier output/2 (carry/2) prescaler control bit prescaler dividing ratio selection bit timer 1 count source selection bits w1 3 w1 2 w1 1 w1 0 0 1 0 1 note: r represents read enabled, and w represents write enabled. (3) timer control register w2 the timer 1 control bit is assigned to the bit 0, and timer 2 count value selection bits are assigned to bits 1 and 2, and the timer 1 control bit is assigned to the bit 3. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. table 2.3.3 shows the timer control register w2. table 2.3.3 timer control register w2 w1 1 0 0 1 1 w1 0 0 1 0 1 timer control register w2 at reset : 1000 2 at power down : C C C 0 2 r/w f(x cin ) prescaler output (orclk) count source underflow occur every 2 14 count underflow occur every 2 13 count not available not available stop (timer 1 state retained) operating timer 2 count source selection bit timer 2 count value selection bits timer 1 control bit w2 3 w2 2 w2 1 w2 0 0 1 note: r represents read enabled, and w represents write enabled. C represents state retained. w2 2 0 0 1 1 w2 1 0 1 0 1 0 1
application 2.3 timers 2-19 4551 group users manual (4) timer control register w3 the timer lc control bit is assigned to the bit 0, and timer lc count source selection bit is assigned to the bit 1. set the contents of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the contents of register w3 to register a. table 2.3.4 shows the timer control register w3. table 2.3.4 timer control register w3 timer control register w3 at reset : 00 2 at power down : state retained r/w bit 3 of timer 2 is output (timer 2 count source divided by 16) system clock (stck) stop (timer lc state retained) operating timer lc count source selection bit timer lc control bit w3 1 w3 0 0 1 0 1 note: r represents read enabled, and w represents write enabled.
application 2.3 timers 2-20 4551 group users manual 2.3.3 timer application examples (1) timer operation: measurement of constant period the constant period by the setting timer count value can be measured. outline: the constant period by the timer 1 underflow signal can be measured. specifications: timer 1 and prescaler divides the system clock frequency f(x in ) = 3.6 mhz, and the timer 1 interrupt request occurs every 4 ms. figure 2.3.2 shows the setting example of the constant period measurement. (2) timer operation: constant period counter by timer 2 the constant period by the setting timer count value can be measured. outline: the correct time can be measured and the clock which has high-accuracy can be set up by using a 32.768 khz quartz-crystal oscillator. specifications: timer 2 divides the sub-clock frequency f(x cin ) = 32.768 khz, and the timer 2 interrupt request occurs every 250 ms. figure 2.3.3 shows the setting example of constant period counter by timer 2. (3) watchdog timer watchdog timer provides a method to reset the system when a program run-away occurs. in the 4551 group, the bit 12 of timer 2 is used for the watchdog timer. accordingly, when the watchdog timer function is set to be valid, execute the wrst instruction at a certain cycle which consists of timer 2s 8191 counts or less. outline: execute the wrst instruction in timer 2s 8192 count at the normal operation. if program runs wild, the wrst instruction is never executed and system reset occurs. specifications: system clock frequency f(x in ) = 3.6 mhz, sub-clock frequency f(x cin ) = 32.768 khz are used, and program run-away is detected by executing the wrst instruction in 250 ms. figure 2.3.1 shows the watchdog timer function, and figure 2.3.4 shows the example of watchdog timer. fig. 2.3.1 watchdog timer function 3fff 16 0000 16 1fff 16 timer 2 value wef flag wdf flag internal reset signal system reset ? ? ? ? ? ? wrst instruction execution wrst instruction execution
application 2.3 timers 2-21 4551 group users manual fig. 2.3.2 constant period measurement setting example 4ms = (3.6 mhz) 5 4 5 3 5 8 5 (149 + 1) b3 b0 0 b3 b0 0 g0 h b3 b0 0 0 1 1 interrupt enable flag inte interrupt control register v1 disable interrupts timer 1 interrupt is temporarily disabled. all interrupts disabled ( di instruction) timer 1 interrupt occur disabled ( tv1a instruction) 0 5 5 5 stop timer operation timer 1 operation is temporarily stopped. timer control register w2 555 timer 1 operation stop ( tw2a instruction) a set timer value timer 1 count time is set. (the formula is shown ] a below.) timer control register w1 timer 1 reload register r1 95 16 prescaler divided by 8 selected ( tw1a instruction) timer count value 149 set ( t1ab instruction) ? clear interrupt request the timer 1 interrupt activated condition is cleared. timer 1 interrupt request flag t1f 0 clear the timer 1 interrupt activated condition ( snzt1 instruction) h note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t1f, insert the nop instruction after the snzt1 instruction. ? start timer 1 operation the timer 1 operation which is temporarily stopped is restarted. timer control register w2 timer 1 operation start ( tw2a instruction) b3 b0 5 1 55 ? enable interrupts the timer 1 interrupt which is temporarily disabled is enabled. interrupt control register v1 interrupt enable flag inte timer 1 interrupt occur enabled ( tv1a instruction) all interrupts enabled ( ei instruction) b3 b0 1 5 55 1 constant period interrupt execution started 5 : it can be 0 or 1. system clock instruction clock prescaler dividing ratio timer 1 count value ] a the prescaler dividing ratio and timer 1 count value to make the interrupt occur every 4ms are set as follows: C1
application 2.3 timers 2-22 4551 group users manual fig. 2.3.3 constant period counter by timer 2 setting example 0.25s = (32. 768kh z) 5 2 13 C1 g0 h b3 b0 0 interrupt enable flag inte interrupt control register v1 disable interrupts timer 2 interrupt is temporarily disabled. all interrupts disabled ( di instruction) timer 2 interrupt occur disabled ( tv1a instruction) 0 5 5 5 b3 b0 01 b3 b0 00 set timer value timer 2 count time is set. (only when timer count value is 2 or 2 , the formula is shown ] a below.) timer count value 2 set ( tw2a instruction) timer count value 2 set ( tw2a instruction) when timer count value = 2 , timer control register w2 when timer count value = 2 , timer control register w2 13 14 13 14 55 55 13 14 a reset timer value and set count source timer 2 counter is initialized. initialization is performed only by setting w2 3 from 0 to 1. timer control register w2 this processing and setting timer value shown can be executed simultaneously. timer control register w2 timer control register w2 b3 b0 0 b3 b0 1 b3 b0 0 55 5 55 5 55 5 timer 2 reset timer 2 count source is returned to x cin . ? clear interrupt request the timer 2 interrupt activated condition is cleared. timer 2 interrupt request flag t2f clear the timer 2 interrupt activated condition ( snzt2 instruction) 0 h note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t2f, insert the nop instruction after the snzt2 instruction. ? enable interrupts the timer 2 interrupt which is temporarily disabled is enabled. interrupt control register v1 interrupt enable flag inte timer 2 interrupt occur enabled ( tv1a instruction) all interrupts enabled ( ei instruction) 1 b3 b0 1 555 constant period interrupt execution started ] a the timer 2 count value to make the interrupt occur every 0.25s is set as follows: 5 : it can be 0 or 1. sub-clock timer 2 count value
application 2.3 timers 2-23 4551 group users manual fig. 2.3.4 watchdog timer setting example g0 h pof2 epof; pof instruction enabled (ram back-up mode) ? ? ? ? ? ? oscillation stop wrst; wdf flag cleared b3 b0 0 set timer 2 count source timer 2 countsource is set. x cin selected ( tw2a instruction) timer control register w2 55 5 activate watchdog timer watchdog timer is activated. watchdog timer enable flag wef 1 watchdog timer enable flag wef set ( wrst instruction) main routine (every 20 ms) wdf flag reset watchdog timer flag wdf is reset. 0 watchdog timer flag wdf cleared ( wrst instruction) main routine execution repeat do not perform the interrupt processing for reset of watchdog timer flag wdf. interrupt may keep operating even when a program runs wild. when going into ram back-up mode in the ram back-up mode, the value of wdf flag is initialized. however, when the wdf flag is 1, at the same time, a microcomputer may be reset. when the watchdog timer and ram back-up mode are used, execute the wrst instruction before system enters into the ram back-up mode in order to initialize the wdf flag. 5 : it can be 0 or 1.
application 2.3 timers 2-24 4551 group users manual 2.3.4 notes on use (1) prescaler stop the prescaler operation to change its frequency dividing ratio. (2) count source ? stop timer 1 or timer lc counting to change its count source. ? when timer 2 count source changes from f(x cin ) to orclk (w2 3 = 0 ? w2 3 = 1), the count value of timer 2 is initialized. however, when timer 2 count source changes from orclk to f(x cin ) (w2 3 = 1 ? w2 3 = 0) or the same count source is set again (w2 3 = 0 ? w2 3 = 0 or w2 3 = 1 ? w2 3 = 1), the count value of timer 2 is not initialized. (3) timer 2 timer 2 has the watchdog timer function (wdt). when timer 2 is used as the wdt, note that the processing to initialize the count value and the execution of the wrst instruction. (4) reading the count value stop the prescaler and then execute the tab1 instruction to read timer 1 data. (5) writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows.
application 2.4 carrier generating circuit 2-25 4551 group users manual 2.4 carrier generating circuit the 4551 group has a carrier generating circuit that generates the transfer waveform by dividing the system clock (stck) for each remote control carrier wave. also, the 4551 group has the function to control the carrier wave output from port carr by using timer 1. this section describes carrier functions, related registers, application examples using each carrier output and notes. 2.4.1 carrier functions (1) carrier wave output carrier wave is selected by the carrier wave selection register c1. carrier output is started with the stcr instruction, and carrier output is stopped with the spcr instruction. (2) carrier wave output auto-control function timer 1 can auto-control the output enable/disable interval of port carr carrier wave by setting register c2.
application 2.4 carrier generating circuit 2-26 4551 group users manual 2.4.2 related registers (1) carrier wave selection register c1 the output waveform of carrier wave is selected. set the contents of this register through register a with the tc1a instruction. figure 2.4.1 shows the relationship between register c1 and carrier wave. fig. 2.4.1 carrier wave selection register duty frequency carrier wave register c1 setting value no carrier wave ??fixed c1 0 c1 1 c1 2 1/4 1/2 1/2 1/3 1/2 output waveform stck/24 stck/16 stcr instruction spcr instruction c1 3 stck/12 stck/8 stck 1/4 1/2 1/2 1/3 1/2 (at reset: 0 1 1 1 2 , at power down: 0 1 1 1 2 , w) carrier wave selection register c1 stck/2 no available ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0001 0010 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 0110 1110 1111 ? ? note:??represents write enabled.
application 2.4 carrier generating circuit 2-27 4551 group users manual (2) carrier wave output control register c2 the carrier wave output auto-control bit is assigned to the bit. set the contents of this register through register a with the tc2a instruction. table 2.4.1 shows the carrier wave output control register c2. table 2.4.1 carrier wave output control register c2 carrier wave output control register c2 at reset : 0 2 at power down : 0 2 w auto-control output by timer 1 is invalid auto-control output by timer 1 is valid carrier wave output auto-control bit c2 0 0 1 note: w represents write enabled. (3) carrier wave generating control flag cr execute the spcr instruction to set the carrier wave generating control flag cr to 0. execute the stcr instruction to set the carrier wave generating control flag cr to 1. table 2.4.2 shows the carrier wave generating control flag cr. table 2.4.2 carrier wave generating control flag cr carrier wave generating control flag cr at reset : 0 2 at power down : 0 2 w carrier wave generating stop ( spcr instruction) carrier wave generating start ( stcr instruction) carrier wave generation control cr 0 1 note: w represents write enabled.
application 2.4 carrier generating circuit 2-28 4551 group users manual 2.4.3 carrier wave output application examples (1) remote control waveform output by carrier wave output auto-control function the carrier wave output auto-control function can be used to turn carrier wave on/off automatically by counting carrier waveform. outline: carry is selected as the timer 1 count source and port carr can be controlled. output of waveform can be controlled by the bit c2 0 . a off interval can be output. specifications: the 37.9 khz carrier wave is output from port carr by using system clock frequency f(x in ) = 3.64 mhz. also, the timer 1 interrupt occurs, and at the same time, setting the next output interval is performed. figure 2.4.2 and figure 2.4.3 show the setting example of carrier wave auto-control, figure 2.4.4 shows the setting example of carrier wave output interval. fig. 2.4.2 carrier wave auto-control setting example 1 b3 b0 0 interrupt control register v1 disable interrupts timer 1 interrupt is temporarily disabled. timer 1 interrupt occur disabled ( tv1a instruction) 5 5 5 stop timer operation and carrier operation timer 1 operation and carrier operation is temporarily stopped. timer control register w2 carrier wave generation control flag cr b3 b0 0 55 5 ? timer 1 operation stopped ( tw2a instruction) carrier wave generation stop ( spcr instruction) a change of count source timer 1 count source is changed. timer control register w1 b3 b0 0 5 5 1 count source carry selected ( tw1a instruction) ? set timer value timer 1 count time is set. (the formula is shown ] a below.) reload register r1 ?4 16 timer count value 20 is set ( t1ab instruction) ? set carrier generation circuit carrier wave frequency and duty ratio are set. carrier wave selectionr register c1 frequency stck/24, duty ratio 1/3 selected ( tc1a instruction) b3 b0 0 0 0 0 continue to figure 2.4.3 on the next page.
application 2.4 carrier generating circuit 2-29 4551 group users manual fig. 2.4.3 carrier wave auto-control setting example 2 8.77 m s 26.3 m s 0.55 ms 37.9 khz = 3.64 mhz 5 1/4 5 1/24 0.55 ms = (37.9 khz) 5 (20+1) -1 from preceding figure 2.4.2. ? set carrier wave output auto-control carrier wave output auto-control is set to be valid. carrier wave output cotrol register c2 0 auto-control valid by timer 1 ( tc2a instruction) 1 ? clear interrupt request the timer 1 interrupt activated condition is cleared. timer 1 interrupt request flag t1f 0 clear the timer 1 interrupt activated condition ( snzt1 instruction) h note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t1f, insert the nop instruction after the snzt1 instruction. ? start timer 1 operation the timer 1 operation which is temporarily stopped is restarted.(timer is stopped because count source is not operating.) timer control register w2 timer 1 operation start ( tw2a instruction) b3 b0 5 1 55 timer 1 interrupt occur enabled ( tv1a instruction) enable interrupts timer 1 interrupt which is temporarily disabled is enabled. interrupt control register v1 b3 b0 1 5 55 start carrier output carrier output is started. (in this time, timer 1 operation is started simultaneously.) carrier wave generating control flag cr carrier wave generating started ( stcr instruction) 1 carrier output started setting the next output waveform set next waveform data the next carrier output length is set to bit c2 0 and reload register r1. interrupt occurs interrupt occurs set next waveform data the next carrier output length is set to bit c2 0 and reload register r1. 11 12 12 repeated 5 : it can be 0 or 1. system clock carrier wave dividing ratio timer 1 count value carrier wave frequency refer to figure 2.4.4 for the detail of setting output data. ] a the carrier wave which duty ratio is 1/3 is output with a 3.64 mhz oscillator for the 0.55 ms.
application 2.4 carrier generating circuit 2-30 4551 group users manual fig. 2.4.4 carrier wave output interval setting example a a a a a aa da c2 0 a aa aad a a 16a 8a a b c d a t s a a a ? ? ? ? ? timer 1 start timer 1 underflow reload register r1 port carr output carrier wave output start ( stcr ) initial value a is set to timer 1. the carrier wave output is started with the stcr instruction. c2 0 is set to 0 to continue the carrier wave output. a after timer 1 underflow is counted to 15 times by software, c2 0 is set to 1. ? after carr output is turned off by timer 1 underflow, c2 0 is set to 0. ? after timer 1 underflow is counted to 7 times by software, c2 0 is set to 1. ? the next carr off interval b is set to reload register r1. ? the next carr output interval c is set to reload register r1. ? the next carr off interval d is set to reload register r1. the next carr output interval a is set to reload register r1. b c b c
application 2.4 carrier generating circuit 2-31 4551 group users manual fig. 2.4.5 carrier wave by software generating example (2) carrier wave generating by software carrier wave generating can be output by software count. outline: the carrier wave generating circuit is set to no carrier wave and carrier wave is generated by software. specifications: the 37.9 khz carrier wave is generated by using main clock frequency f(x in ) = 3.64 mhz. figure 2.4.5 shows the generating example of carrier wave by software. stcr nop spcr nop nop nop nop nop nop nop nop stcr spcr stck carr output 1.10 m s 1 instruction (3.30 m s) b3 b0 1 0 1 0 set carrier wave output auto-control carrier wave output auto-control is set to be invalid. carrier wave output control register c2 0 ? auto-control by timer 1 invalid ( tc2a instruction) set carrier generation circuit carrier wave frequency and duty ratio is set. carrier wave selection register c1 no carrier wave ( tc1a instruction) a start carrier output carrier output is started. description instruction example 8.79 m s 17.58 m s
application 2.4 carrier generating circuit 2-32 4551 group users manual 2.4.4 notes on use (1) note on the carrier generating circuit stop in order to stop the carrier wave which has the cycle longer than that of the instruction clock with the spcr instruction, stop it at the point when the carrier wave outputs l level in the spcr instruction execution cycle. if this condition is not satisfied, the last h output interval of carrier wave is shortened. (2) notes when using the carrier wave output auto-control function l execute the stcr instruction after setting the timer 1 and register c2 in order to start the carrier generating circuit operation. l stop the timer 1 (w2 0 =0) after stopping the carrier generating circuit ( spcr instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. l if the carrier wave output auto-control function is invalidated (c2 0 =0) while the carrier wave output is auto-controlled, the output of port carr retains the state when the auto-control is invalidated regardless of timer 1 underflow. this state can be terminated by timer 1 stop (w2 0 =0). when the carrier wave output auto-control function is validated (c2 0 =1) again after it is invalidated (c2 0 =0), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. however, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. l use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto-control function is selected. if the orclk is used as the count source, a hazard wave may occur in port carr output because orclk is not synchronized with the carrier wave. l when no carrier wave is selected with register c1 ((c1 3 c1 2 c1 1 c1 0 ) = (0101), (1101)), the disable/enable of the carrier wave output cannot be controlled by the carrier wave output auto- control function.
application 2.5 lcd function 2-33 4551 group users manual duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 maximum number of displayed pixels 40 segments 60 segments 80 segments used com pins com 0 , com 1 ( note ) com 0 Ccom 2 ( note ) com 0 Ccom 3 ( note ) table 2.5.1 duty and maximum number of displayed pixels 2.5 lcd function the 4551 group has an lcd (liquid crystal display) controller/driver. 4 common signal output pins and 20 segment signal output pins can be used to drive the lcd. by using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. this section describes the lcd operation description, related registers, application examples using the lcd and notes. 2.5.1 operation description (1) lcd duty and bias control table 2.5.1 shows the duty and maximum number of displayed pixels. use bits 0 and 1 of lcd control register (l1) to select the proper display method for the lcd panel being used. also, when using segment pins are 19 or less, seg 16 Cseg 19 can be used as an i/o port with register l2. note: leave unused com pins open. (2) lcd drive timing the frequency (f) of the lcd clock generating the lcd drive timing and frame frequency are shown below. figure 2.5.1 shows the structure of the lcd clock circuit. l when the prescaler output (orclk) is used for the timer 2 count source (w2 3 = 1) f = orclk 55 5 a ? ? l when f(x cin ) is used for the timer 2 count source (w2 3 = 0) f = f(x cin ) 5 5 a?? the frame frequency for each display method can be obtained by the following formula. frame frequency = (hz) frame period = (s) [f: frame frequency, 1/n: duty] 1 16 1 lc + 1 1 2 1 16 1 lc + 1 1 2 f n n f fig. 2.5.1 lcd clock control circuit structure ? ? 1/2 1/16 w3 0 0 1 ( note 1 ) x cin w2 3 0 1 orclk stck w3 1 1 0 ( note 2 ) timer 2 a timer lc lcd clock notes 1: count source is stopped by clearing w3 0 to 0. 2: when the lcd function is used, set w3 1 to 0. 5
application 2.5 lcd function 2-34 4551 group users manual (3) lcd display method the 4551 group has the lcd ram area for the lcd display. when 1 is written to a bit in the lcd ram data, the display pixel which correspond to the bit automatically turns on. figure 2.5.2 shows the lcd ram map. fig. 2.5.2 lcd ram map 2.5.2 related registers (1) lcd control register l1 the lcd duty and bias selection bits are assigned to bits 0 and 1. the lcd on/off bit is assigned to the bit 2. set the contents of this register through register a with the tl1a instruction. the tal1 instruction can be used to transfer the contents of register l1 to register a. table 2.5.2 shows the lcd control register l1. table 2.5.2 lcd control register l1 lcd control register l1 at reset : 0000 2 at power down : state retained r/w not used lcd on/off bit lcd duty and bias selection bits l1 3 l1 2 l1 1 l1 0 0 1 0 1 note: r represents read enabled, and w represents write enabled. duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 l1 1 0 0 1 1 l1 0 0 1 0 1 this bit has no function, but read/write is enabled. off on not available z x y 8 9 10 11 12 13 14 15 com 1 01 2 3 210 3 210 3 210 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 3 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 2 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 1 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 0 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 0 seg 0 seg 0 seg 0 seg 8 seg 17 seg 18 seg 19 seg 16 seg 8 seg 8 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 17 seg 18 seg 19 seg 16 seg 17 seg 18 seg 19 seg 16 seg 17 seg 18 seg 19 seg 16 bit note: lcd display ram is not assigned.
application 2.5 lcd function 2-35 4551 group users manual (2) lcd control register l2 port p2 function and segment pin function of pins p2 0 /seg 16 Cp2 3 /seg 19 can be switched by setting register l2. set the contents of this register through register a with the tl2a instruction. table 2.5.3 shows the lcd control register l2. table 2.5.3 lcd control register l2 lcd control register l2 at reset : 1111 2 at power down : state retained w seg 19 p2 3 seg 18 p2 2 seg 17 p2 1 seg 16 p2 0 p2 3 /seg 19 function switch bit p2 2 /seg 18 function switch bit p2 1 /seg 17 function switch bit p2 0 /seg 16 function switch bit l2 3 l2 2 l2 1 l2 0 0 1 0 1 0 1 0 1 note: w represents write enabled. (3) timer control register w3 the timer lc control bit is assigned to the bit 0, and the timer lc count source selection bit is assigned to the bit 1. when the lcd display function is used, set the bit 1 to 0. set the contents of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the contents of register w3 to register a. table 2.5.4 shows the timer control register w3. table 2.5.4 timer control register w3 timer control register w3 at reset : 00 2 at power down : state retained r/w bit 3 of timer 2 is output (timer 2 count source divided by 16) system clock (stck) stop (timer lc state retained) operating timer lc count source selection bit timer lc control bit w3 1 w3 0 0 1 0 1 note: r represents read enabled, w represents write enabled.
application 2.5 lcd function 2-36 4551 group users manual 2.5.3 lcd application examples (1) lcd display lcd display function can be used to display 80 pixels (maximum 4 common 5 20 segment). outline: lcd can be displayed easily by using the lcd display function. specifications: 1/4 duty and 1/3 bias lcd is displayed by using lcd display panel example. timer 2 is used for the lcd clock source, the sub-clock f(x cin ) = 32.768 khz is used for the timer 2 clock source, and the frame frequency is set to 85 hz. figure 2.5.3 shows the lcd display panel example, figure 2.5.4 shows the segment assignment example, figure 2.5.5 shows the lcd ram assignment example, and table 2.5.5 shows the frame frequency. fig. 2.5.3 lcd display panel example fig. 2.5.4 segment assignment example fig. 2.5.5 lcd ram assignment example z x y 8 9 10 11 12 13 14 15 com 1 012 3 210 3 210 3 21 0 com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 g d a b c e f bit -g -g a -g ? -g ? -g ? -g ? -g ? -g -e -e a -f ? -e ? -e ? -e ? -e ? -e -d -d a -d ? -d ? -d ? -d ? -d ? -d -c -c a -c ? -c ? -c ? -c ? -c ? -c -f -f a -f ? -f ? -f ? -f ? -f ? -f -b -b a -b ? -b ? -b ? -b ? -b ? -b -a -a a -a ? -a ? -a ? -a ? -a ? -a start stop unused unused unused unused ? ? ? ? su. tu. sp program mo. fr. ep a.m. tu. sa. ch p.m. we. bs every weeks note: lcd display ram is not assigned. p r o g r a m a . m . p . m . c h e p s p s t a r t s t o p b s s u . m o . t u . w e . t h . f r . s a . e v e r y w e e k s a ? ?? ? ? p r o g r a m a . m . p . m . c h e p s p s t a r t s t o p b s s u . m o . t u . w e . t h . f r . s a . e v e r y w e e k s
application 2.5 lcd function 2-37 4551 group users manual fig. 2.5.6 initial setting example b1 b0 01 b3 b0 0 0 0 0 2 16 1 16 1 (2+1) 2 1 4 1 85.3 hz = (32.768 khz) 5555 b3 b0 1 1 5 5 b3 b0 5 5 1 5 ? initialization of lcd display ram lcd display ram is initialized. initial data is set. lcd display ram b1 b0 5 0 initialization (refer to section 2.3 timer.) operate timer 2 timer 2 count source is set to f(x cin ). set seg 16 Cseg 19 p2 0 /seg 16 Cp2 3 /seg 19 are set to output. lcd control register l2 seg 16 Cseg 19 selected ( tl2a instruction) a stop timer lc timer lc operation is stopped. timer control register w3 timer lc stopped ( tw3a instruction) ? set timer lc timer lc value is set. (the formula is shown ] a below.) timer lc reload register rlc timer lc tlc timer count value 2 is set. ( tlca instruction) ? set lcd display method lcd duty and bias are set. lcd control register l1 1/4 duty and 1/3 bias set. ( tl1a instruction) ? set timer lc count source timer lc count source is changed. timer control register w3 count source is set to bit 3 of timer 2 . timer lc start ( tw3a instruction) ? display lcd lcd display function is set to be valid. lcd control register lc lcd turned on ( tl1a instruction) to normal program ] a the timer lc count value when the frame frequency is set to 85.3 hz is set as follows: 5 : it can be 0 or 1. display changed by rewriting lcd display ram sub-clock bit 3 of timer 2 timer lc duty ratio
application 2.5 lcd function 2-38 4551 group users manual note: values in the table shows the frame frequency (however, the values are rounded off to the decimal points). 2.5.4 notes on use (1) timer lc count source stop each timer counting to change timer lc count source. table 2.5.5 frame frequency lcd clock = x cin : 32.768 khz lcd timer value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 duty 1/2 512 hz 256 hz 171 hz 128 hz 102 hz 85 hz 73 hz 64 hz 57 hz 51 hz 47 hz 43 hz 39 hz 37 hz 34 hz 32 hz 1/3 341 hz 170 hz 114 hz 85 hz 68 hz 57 hz 49 hz 42 hz 38 hz 34 hz 31 hz 28 hz 26 hz 24 hz 23 hz 21 hz 1/4 256 hz 128 hz 85 hz 64 hz 51 hz 43 hz 37 hz 32 hz 28 hz 27 hz 23 hz 21 hz 20 hz 18 hz 17 hz 16 hz lcd timer value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1/2 1185 hz 592 hz 395 hz 296 hz 237 hz 197 hz 169 hz 148 hz 131 hz 118 hz 108 hz 99 hz 91 hz 85 hz 79 hz 74 hz 1/3 790 hz 395 hz 263 hz 197 hz 158 hz 132 hz 113 hz 99 hz 88 hz 79 hz 72 hz 66 hz 61 hz 56 hz 53 hz 49 hz 1/4 592 hz 296 hz 197 hz 148 hz 118 hz 99 hz 85 hz 74 hz 66 hz 59 hz 54 hz 49 hz 46 hz 42 hz 39 hz 37 hz lcd timer value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1/2 592 hz 296 hz 197 hz 148 hz 118 hz 99 hz 85 hz 74 hz 66 hz 59 hz 54 hz 49 hz 46 hz 42 hz 39 hz 37 hz 1/3 395 hz 197 hz 132 hz 99 hz 79 hz 66 hz 56 hz 49 hz 44 hz 39 hz 36 hz 33 hz 30 hz 28 hz 26 hz 25 hz 1/4 296 hz 148 hz 99 hz 74 hz 59 hz 49 hz 42 hz 37 hz 33 hz 30 hz 27 hz 25 hz 23 hz 21 hz 20 hz 18 hz duty duty lcd clock = orclk: 910 khz/12 or = orclk:3.64 mhz/48 lcd clock = orclk: 910 khz/24 or = orclk:3.64 mhz/96
application 2-39 4551 group users manual 2.6 power down function 2.6 power down function the 4551 group has the clock operation mode and ram back-up mode for the power down function. the 4551 group enters 12 kinds of state which includes the reset state to reduce the power dissipation. figure 2.6.1 shows the state transition, and figure 2.6.2 shows the oscillation stabilizing time. in this section, the clock control function, each power down function, related register and application example for the power down function are described. fig. 2.6.1 state transition stabilizing time a : an interval required to stabilize the f(x in ) oscillation is automatically generated by hardware. stabilizing time b : an interval required to stabilize the f(x cin ) oscillation is automatically generated by hardware. stabilizing time c : generate an interval required to stabilize the f(x in ) oscillation in state c or g by software at the transition d ? c, d ? g, h ? c, h ? g, j ? c, or j ? g. stabilizing time d : generate an interval required to stabilize the f(x cin ) oscillation in state b, f by software at the transition a ? b, e ? f, a ? f, or e ? b. return input 1: external wakeup signal (p0 0 Cp0 3 , p1 0 Cp1 3 ) return input 2: timer 2 interrupt request flag notes 1. mr 3 =1 ? the microcomputer starts its operation after counting f(x cin ) clock signal 59 to 70 times. mr 3 =0 ? the microcomputer starts its operation after counting f(x cin ) clock signal 32 to 43 times. 2. when the following 2 conditions are satisfied, the transition a ? e, b ? f, a ? f, c ? f, g ? f represented by can be executed. (1) v dd = 2.2 v to 5.5 v (one time prom version: v dd = 2.5 v to 5.5 v), f(x in ) 1.0 mhz (2) v dd = 4.5 v to 5.5 v, f(x in ) 2.0 mhz mr 0 ? 0 b mr 0 ? 1 c mr 1 ? 1 mr 1 ? 0 d k a mr 2 ? 1 mr 0 ? 0 f mr 0 ? 1 g mr 1 ? 1 mr 1 ? 0 h mr 2 ? 0 e mr 2 ? 1 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 3 ? 0 (note 2) (note 2) (stabilizing time c ) j f(x in ):stop f(x cin ) : oscillation i (stabilizing time c ) (stabilizing time d ) (stabilizing time d ) b , f c , g d , h b , f c , g d , h a , e a , e b , f c , g d , h b , f c , g d , h a , e (note 2) reset pof execution return input 1 (stabilizing time a ) pof execution return input 1, 2 (stabilizing time a ) pof execution return input 1, 2 (stabilizing time c ) (note 1) clock operating mode pof execution return input 1, 2 (stabilizing time c ) (note 1) f(x in ):stop f(x cin ):stop clock operating mode f(x in ):oscillation f(x cin ):stop system clock; f(x in )/4 mr=(1000 2 ) mr 2 ? 0 f(x in ):oscillation f(x cin ):oscillation f(x in ):oscillation f(x cin ):oscillation f(x in ):stop f(x cin ):oscillation system clock; f(x in )/4 mr=(1100 2 ) system clock; f(x cin )/4 mr=(1101 2 ) system clock; f(x cin )/4 mr=(1111 2 ) f(x in ):oscillation f(x cin ):stop system clock; f(x in ) mr=(0000 2 ) f(x in ):oscillation f(x cin ):oscillation system clock; f(x in ) mr=(0100 2 ) f(x in ):oscillation f(x cin ):oscillation system clock; f(x cin ) mr=(0101 2 ) f(x in ):stop f(x cin ):oscillation system clock; f(x cin ) mr=(0111 2 ) (stabilizing time d ) (note 2) pof2 execution return input 1 (stabilizing time a ) pof2 execution return input 1 (stabilizing time a ) pof2 execution return input 1 (stabilizing time b ) pof2 execution return input 1 (stabilizing time b ) f(x in ):stop f(x cin ):stop ram back-up mode a , e mr 2 ? 0 mr 3 ? 0 mr 2 ? 1 mr 3 ? 1 (note 2) mr 2 ? 1 mr 2 ? 0 mr 3 ? 0 mr 3 ? 1 mr 3 ? 1 mr 0 ? 0 mr 3 ? 0 mr 0 ? 1 mr 0 ? 1 mr 0 ? 0 mr 3 ? 1 mr 3 ? 0 mr 3 ? 1 mr 1 ? 0 mr 3 ? 0 mr 1 ? 1 mr 1 ? 0 mr 3 ? 0 mr 1 ? 1 mr 3 ? 1 (stabilizing time c ) (stabilizing time d ) (stabilizing time c )
application 2-40 4551 group users manual 2.6 power down function fig. 2.6.2 oscillation stabilizing time in each mode mr 3 =1: f(x cin ) is counted 59 to 70 times. mr 3 =0: f(x cin ) is counted 32 to 43 times. l oscillation stabilizing time a f(x in ) ( note ) oscillation condition satisfied f(x in ) is counted 10757 to 10786 times. software start (address 0 in page 0) l oscillation stabilizing time b f(x cin ) ( note ) oscillation condition satisfied l oscillation stabilizing time c (software operating) oscillation condition satisfied f(x in ) is counted 10757 to 10786 times. software start (address 0 in page 0) f(x cin ) f(x in ) oscillation stabilizing time is generated by software. f(x in ) available l oscillation stabilizing time c (when returning from clock operating mode to state c, g) f(x cin ) f(x in ) return input f(x in ) available f(x in ) oscillation wait time by software software start (address 0 in page 0) l oscillation stabilizing time d f(x in ) f(x cin ) oscillation condition satisfied f(x cin ) available f(x cin ) oscillation stabilizing time is generated by software. note : time until 4551 group recognize oscillation. expresses system clock. f(x in )
application 2-41 4551 group users manual 2.6 power down function 2.6.1 clock control function the 4551 group can reduce the power dissipation by controlling oscillation with the clock control register mr. refer to section 3.1 electrical characteristics for the oscillation frequency and power dissipation. in figure 2.6.1, directions in which state transition can be executed are expressed by the arrow. for example, execute the transition a ? b ? ((x cin ) oscillation stabilizing wait) ? g ? h to execute the transition from the state a (mr 3 mr 2 mr 1 mr 0 = 1000) after reset to the state h (mr 3 mr 2 mr 1 mr 0 = 0111). note: do not stop the oscillation circuit selected by clock selection bit (mr 0 ). note the stop of the oscillation circuit selected with the clock selection bit (mr 0 ) if the following setting is performed. example 1: (mr 3 mr 2 mr 1 mr 0 ) = ( 5 0 5 1) (f(x cin ) selected, f(x cin ) oscillation stop) example 2: (mr 3 mr 2 mr 1 mr 0 ) = ( 55 10) (f(x in ) selected, f(x in ) oscillation stop) 5 : 0 or 1. 2.6.2 power down function when the pof instruction or pof2 instruction is executed just after the epof instruction, system enters the power down state. table 2.6.1 shows the internal state at each mode. also, table 2.6.2 shows the return source from this state. (1) clock operating mode in this mode, current dissipation can be reduced by stopping x in -x out oscillation and system clock with the states of ram, reset circuit, x cin Cx cout oscillation, lcd display and timer 2 retained. (2) ram back-up mode as oscillation stops with ram, the state of reset circuit retained, current dissipation can be reduced without losing the contents of ram.
application 2-42 4551 group users manual 2.6 power down function function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) ( note 2 ) contents of ram port level clock control register mr timer control register w1 timer control registers w2, w3 interrupt control register v1 interrupt control register i1 carrier wave control registers and flag (c1, c2, cr) lcd display function lcd control registers l1, l2 timer lc timer 1 function timer 2 function external 0 interrupt request flag (exf0) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) watchdog timer flag (wdf) watchdog timer enable flag (wef) interrupt enable flag (inte) general-purpose register v2 notes 1: o represents that the function can be retained, and 5 represents that the function is initialized. registers and flags other than the above are undefined at power down, and set an initial value after returning from power down state. 2: the stack pointer (sp) points the level of the stack register and is initialized to 111 2 at power down. 3: lcd is turned off. 4: the state of timer is undefined. ram back-up 5 o o o 5 o 5 o 5 ( note 3 ) o ( note 4 ) 5 o 5 5 o 5 o 5 5 clock operating 5 o o o 5 o 5 o 5 o o o 5 o 5 5 o o o 5 5 table 2.6.1 functions and states retained at ram back-up mode and the clock operating mode
application 2-43 4551 group users manual 2.6 power down function remarks port p0 shares the falling edge detection circuit with port p1. the key-on wakeup function of port p0 is always valid. the only key-on wakeup function of the port p1 bit of which the pull-up transistor is turned on is valid. set all the port using the key-on wakeup function to h level before going into the power down state. the timer 2 interrupt request flag (t2f) can be used only when system returns from the clock operating mode ( pof instruction execution). however, if the pof and pof2 instructions are executed while the t2f flag = 1, its operation is recognized as the return condition and system returns from the clock operating mode. timer 2 interrupt request flag return condition returns by an external falling edge input (h ? l). returns by timer 2 underflow and setting t2f flag to 1. table 2.6.2 return source and return condition note: p1 pin has the pull-up transistor which can be turned on/off by software. (3) start condition identification when system returns from both power down and reset, software is started from address 0 in page 0. the start condition (warm start or cold start) can be identified by examining the state of the power down flag (p) with the snzp instruction. also, warm start condition (timer 2 or external wakeup signal) can be identified by the state of the t2f flag. table 2.6.3 shows the start condition identification, and figure 2.6.3 shows the start condition identified example. table 2.6.3 start condition identification fig. 2.6.3 start condition identified example return source ports p0, p1 external wakeup signal return condition external wakeup signal input timer 2 interrupt request flag reset p flag 1 1 0 t2f flag 1 1 0 software start p = 1 t2f = 1 ? ? no yes yes return by external wakeup si g nal return by timer 2 underflow cold start no
application 2-44 4551 group users manual 2.6 power down function 2.6.3 related register (1) clock control register mr clock control register mr controls the system clock. set the contents of this register through register a with the tmra instruction. the tamr instruction can be used to transfer the contents of register mr to register a. table 2.6.4 shows the clock control register mr. table 2.6.4 clock control register mr clock control register mr at reset : 1000 2 at power down : state retained r/w mr 0 =0 f(x in ) mr 0 =1 f(x cin ) mr 0 =0 f(x in )/4 mr 0 =1 f(x cin )/4 f(x cin ) oscillation stop, ports d 6 and d 7 selected f(x cin ) oscillation enabled, ports d 6 and d 7 not selected oscillation enabled oscillation stop f(x in ) f(x cin ) system clock (stck) selection bit f(x cin ) oscillation circuit control bit f(x in ) oscillation circuit control bit clock selection bit 0 1 0 1 0 1 0 1 mr 3 mr 2 mr 1 mr 0 note: r represents read enabled, and w represents write enabled. (2) pull-up control register pu0 pull-up control register pu0 controls the pull-up function and key-on wakeup function. set the contents of this register through register a with the tpu0a instruction. the tapu0 instruction can be used to transfer the contents of register pu0 to register a. table 2.6.5 shows the pull-up control register pu0. table 2.6.5 pull-up control register pu0 pull-up control register pu0 at reset : 0000 2 at power down : state retained r/w pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup pull-up transistor off, no key-on wakeup pull-up transistor on, key-on wakeup port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu0 3 pu0 2 pu0 1 pu0 0 note: r represents read enabled, and w represents write enabled.
application 2-45 4551 group users manual 2.6 power down function 2.6.4 power down function application example (1) clock display a clock which is high-accuracy and low-power dissipation can be set up by using a 32.768 khz quartz-crystal as a sub-clock and executing the pof instruction. outline: the power dissipation can be reduced by using the pof instruction. specifications: time is displayed by the lcd and a 32.768 khz quartz-crystal oscillator. the main routine is executed by key input. figure 2.6.4 shows the software setting example. fig. 2.6.4 software setting example software start address 0 in page 0 initialization of register z yes no p = ??? warm start initiai setting cold start initial setting t2f = ??? yes no clock counter + 1 time display renewed yes no key input ? main routine initial setting di epof pof to main routine 2.6.5 notes on use (1) key-on wakeup function after setting ports (p1 specified with register pu0 and p0) which key-on wakeup function is valid to h, execute the pof or pof2 instruction. l level is input to the falling edge detection circuit even if one of ports which key-on wakeup function is valid is in the l level state, and the edge is not detected. (2) power down instruction execute the pof or pof2 instruction immediately after executing the epof instruction to enter the power down state. note that system cannot enter the power down state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instruction. (3) pof2 instruction if the pof and pof2 instructions are executed while the t2f flag = 1, its operation is recognized as the return condition and system returns from power down state.
application 2-46 4551 group users manual 2.7 reset 2.7 reset system reset is performed by applying l level to the reset pin for 1 machine cycle or more when the following conditions are satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions, oscillation is stabilized. then when h level is applied to the reset pin, the software starts from address 0 in page 0 after elapsing the internal oscillation stabilizing time (f(x in ) is counted 10757 to 10786 machine cycles). figure 2.7.3 shows the oscillation stabilizing time. 2.7.1 reset circuit the 4551group has the power-on reset circuit and voltage drop detection circuit. (1) power-on reset reset can be performed automatically at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, set the time until the supply voltage rises to the minimum operation voltage to 100 m s or less. when the rising time exceeds 100 m s, connect a capacitor between the reset pin and v ss at the shortest distance, input l level to reset pin until the supply voltage reaches the minimum operation voltage. figure 2.7.1 shows the power-on reset example and figure 2.7.2 shows the reset circuit example when the supply voltage rising time exceeds 100 m s. fig. 2.7.1 power-on reset circuit example v dd power-on reset circuit output voltage internal reset signal power-on reset pin wef watchdog timer output internal reset signal reset state reset released this symbol represents a parasitic diode. note: applied potential to reset pin must be v dd or less. ( note ) power-on reset circuit pull-up transistor voltage drop detection circuit l l
application 2-47 4551 group users manual 2.7 reset fig. 2.7.2 reset circuit example when the supply voltage rising time exceeds 100 m s fig. 2.7.3 oscillation stabilizing time after system is released from reset note: keep the value of supply voltage the minimum value or more of the recommended operating conditions. reset software start (address 0 in page 0) reset input 1machine cycle or more = 0.3v dd f(x in ) is counted 10757 to 10786 times ( note ) 0.85v dd reset pin wef watchdog timer output internal reset signal this symbol represents a parasitic diode. note: applied potential to reset pin must be v dd or less. ( note ) power-on reset circuit pull-up transistor voltage drop detection circuit calculate the capacitor value to input ??level until the supply voltage reaches the minimum operation voltage. a
application 2-48 4551 group users manual 2.7 reset 2.7.2 internal state at reset figure 2.7.4 shows the internal state at reset. the contents of timers, registers, flags and ram other than shown in figure 2.7.4 are undefined, so set them to initial values. fig. 2.7.4 internal state at reset ? program counter (pc) ............................................................................................ address 0 in page 0 is set to program counter. ? interrupt enable flag (inte) ................................................................................... ? power down flag (p) ............................................................................................... ? external 0 interrupt request flag (exf0) ................................................................ ? interrupt control register v1 ................................................................................... ? interrupt control register i1 .................................................................................... ? timer 1 interrupt request flag (t1f) ...................................................................... ? timer 2 interrupt request flag (t2f) ...................................................................... ? watchdog timer flag (wdf) ................................................................................... ? watchdog timer enable flag (wef) ....................................................................... ? timer control register w1 ...................................................................................... ? timer control register w2 ...................................................................................... ? timer control register w3 ...................................................................................... ? clock control register mr ...................................................................................... ? carrier wave selection register c1 ........................................................................ ? carrier wave output control register c2 ................................................................. ? carrier wave generating control flag cr ............................................................... ? lcd control register l1 .......................................................................................... ? lcd control register l2 .......................................................................................... ? pull-up control register pu0 ................................................................................... ? general-purpose register v2 ................................................................................. ? carry flag (cy) ....................................................................................................... ? register a .............................................................................................................. ? register b .............................................................................................................. ? register d .............................................................................................................. ? register e .............................................................................................................. ? data pointer x ........................................................................................................ ? data pointer y ........................................................................................................ ? data pointer z ........................................................................................................ ? stack pointer (sp) .................................................................................................. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 (interrupt disabled) 0000 0 0 0 0 0 0 0 0 (prescaler stopped) 0 0 0 0 (timer 1 stopped) 0 0 (timer lc stopped) 1000 0111 0 0 (carrier wave output disabled) 0 0 0 0 (lcd off) 1 1 1 1 (port p2 selected) 0000 0000 0 0000 0000 555 0000 0000 55 111 5 represents undefined. 55555555
application 2-49 4551 group users manual 2.7 reset 2.7.3 voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. figure 2.7.5 shows the voltage drop detection reset circuit, and figure 2.7.6 shows the operation waveform example of the voltage drop detection circuit. fig. 2.7.5 voltage drop detection reset circuit fig. 2.7.6 voltage drop detection circuit operation waveform v dd reset voltage ( note ) internal reset signal the microcomputer starts operation after the f(x in ) is counted 10757 to 10786 times. note: refer to section ?.1 electrical characteristics?for the reset voltage of the voltage drop detection circuit. reset pin wef watchdog timer output internal reset signal power-on reset circuit pull-up transistor voltage drop detection circuit
application 2-50 4551 group users manual 2.8 oscillation circuit 2.8 oscillation circuit the 4551 group has an internal oscillation circuit to produce the clock required for microcomputer operation. the clock signal f(x in ) is obtained by connecting a ceramic resonator to x in pin and x out pin. the clock signal f(x cin ) is obtained by connecting a quartz-crystal oscillator to x cin pin and x cout pin. 2.8.1 oscillation circuit (1) f(x in ) clock generating circuit the clock signal f(x in ) is obtained by connecting a ceramic resonator externally. connect this external circuit to pins x in and x out at the shortest distance. a feed-back resistor is built-in between x in pin and x out pin. figure 2.8.1 shows an example of an oscillation circuit connecting a ceramic resonator externally. keep the maximum value of oscillation frequency within the range listed table 2.8.1. (2) f(x cin ) clock generating circuit the clock signal f(x cin ) is obtained by connecting a quartz-crystal externally. connect this external circuit to pins x cin and x cout at the shortest distance. a feed-back resistor is built-in between x cin pin and x cout pin. figure 2.8.2 shows an example of an oscillation circuit connecting a quartz-crystal externally. fig. 2.8.2 oscillation circuit example connecting quartz-crystal externally supply voltage 4.5 v to 5.5 v 4.5 v to 5.5 v 2.2 v to 5.5 v ( note ) 2.5 v to 5.5 v ( note ) (system clock) (f(x in )/4) (f(x in )) (f(x in )/4) (f(x in )) oscillation frequency 8.0 mhz 2.0 mhz 4.0 mhz 1.0 mhz note: 2.5 v to 5.5 v for the one timer prom version. table 2.8.1 maximum value of oscillation frequency and supply voltage fig. 2.8.1 oscillation circuit example connecting ceramic resonator externally m34551 x in x out rd c in c out m34551 x cin x cout rd c in c out note: externally connect a damping resistor rd de- pending on the oscilla- tion frequency. (a feed- back resistor is built-in.) use the resonator manufacturers recom- mended value because constants such as ca- pacitance depend on the resonator. note: externally connect a damping resistor rd de- pending on the oscilla- tion frequency. (a feed- back resistor is built-in.) use the quartz-crystal oscillator manufacturers recommended value be- cause constants such as capacitance depend on the oscillator.
application 2-51 4551 group users manual 2.8 oscillation circuit 2.8.2 oscillation operation system clock is supplied to cpu and peripheral device as the standard clock for the microcomputer operation. for the 4551 group, the clock (f(x in )), (f(x in )/4), (f(x cin )), or (f(x cin ))/4 which is supplied from the oscillation circuit is selected with the register mr. figure 2.8.3 shows the structure of the clock control circuit. fig. 2.8.3 structure of clock control circuit 2.8.3 notes on use (1) value of a part connected to an oscillator values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. accordingly, consult the oscillator manufacturer for values of each part connected the oscillator. osc x in x out osc x cin x cout internal clock generating circuit (divided by 3) mr0 r s q r s q pof instruction pof2 instruction mr1 t2f flag falling detected ports p0, p1 reset multiplexer frequency dividing circuit (divided by 4) mr3 0 1 stck instck
application 2-52 4551 group users manual 2.8 oscillation circuit memo
chapter 3 chapter 3 appendix 3.1 electrical characteristics 3.2 typical characteristics 3.3 list of precautions 3.4 notes on noise 3.5 mask rom confirmation form 3.6 rom programming confirmation form 3.7 mark specification form 3.8 package outline
appendix 3-2 4551 group users manual parameter supply voltage input voltage p0, p1, p2, reset , x in , x cin output voltage p0, p1, d output voltage carr, x out , x cout output voltage seg, com power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state symbol v dd v i v o v o v o pd topr tstg ratings C0.3 to 7.0 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to v dd +0.3 300 C20 to 70 C40 to 125 unit v v v v v mw c c 3.1 electrical characteristics 3.1 electrical characteristics 3.1.1 absolute maximum ratings table 3.1.1 absolute maximum ratings
4551 group users manual appendix 3-3 min. 2.2 2.5 4.5 2.0 0.8v dd 0.7v dd 0.85v dd 0.8v dd 0 0 0 0 1.15 1.30 1.00 1.15 3.1.2 recommended operating conditions table 3.1.2 recommended operating conditions (mask rom version:ta = C20 c to 70 c, v dd = 2.2 v to 5.5 v, unless otherwise noted) (one time prom version:ta = C20 c to 70 c, v dd = 2.5 v to 5.5 v, unless otherwise noted) parameter supply voltage ram back-up voltage supply voltage h level input voltage p0, p1, p2 h level input voltage x in h level input voltage reset h level input voltage int l level input voltage p0, p1, p2 l level input voltage x in l level input voltage reset l level input voltage int l level peak output current p0, p1, d 0 Cd 7 , carr l level average output current p0, p1, d 0 Cd 7 , carr ( note ) h level peak output current carr h level average output current carr ( note ) f(x cin ) clock frequency voltage drop detection circuit valid power supply rising time for power-on reset circuit limits symbol v dd v ram v ss v ih v ih v ih v ih v il v il v il v il i ol (peak) i ol (avg) i oh (peak) i oh (avg) f(x cin ) v det t pon max. 5.5 5.5 5.5 5.5 v dd v dd v dd v dd 0.3v dd 0.3v dd 0.3v dd 0.2v dd 10 4 5 2 C30 C15 C15 C7 50 2.15 2.00 2.00 1.85 100 typ. 0 1.65 1.50 unit v v v v v v v v v v v ma ma ma ma khz v m s conditions f(x in ) 4.0 mhz, ceramic resonator, stck=f(x in )/4 f(x in ) 1.0 mhz, ceramic resonator, stck=f(x in ) f(x in ) 4.0 mhz, ceramic resonator, stck=f(x in )/4 f(x in ) 1.0 mhz, ceramic resonator, stck=f(x in ) f(x in ) 8.0 mhz, ceramic resonator, stck=f(x in )/4 f(x in ) 2.0 mhz, ceramic resonator, stck=f(x in ) ram back-up v dd =5.0 v v dd =3.0 v v dd =5.0 v v dd =3.0 v v dd =5.0 v v dd =3.0 v v dd =5.0 v v dd =3.0 v quartz-crystal oscillator mask rom version one time prom version mask rom version v dd = 0 to 2.2 v one time prom version v dd = 0 to 2.5 v mask rom version one time prom version note: the average output current is the average current value at the 100 ms interval. 3.1 electrical characteristics
appendix 3-4 4551 group users manual unit v v m a m a m a ma m a m a m a k w k w v v k w k w k w max. 0.9 0.9 1 1 5.0 65 20 1.0 10 125 250 70 130 6.5 8 9 11 1200 3.1.3 electrical characteristics table 3.1.3 electrical characteristics (mask rom version:ta = C20 c to 70 c, v dd = 2.2 v to 5.5 v, unless otherwise noted) (one time prom version:ta = C20 c to 70 c, v dd = 2.5 v to 5.5 v, unless otherwise noted) limits symbol v ol v oh i ih i il i oz i dd r ph v t+ C v tC r com r seg r vlc parameter l level output voltage p0, p1, d 0 Cd 7 , carr, reset h level output voltage carr h level input current p0, p1, p2, reset l level input current p1, p2 output current at off-state d 0 Cd 7 supply current ( note 2 ) pull-up resistor value hysteresis com output impedance seg output impedance lcd power supply internal resistor value ( note 3 ) test conditions i ol = 5 ma i ol = 2 ma i oh = C15 ma i oh = C7 ma v i = v dd ( note 1 ) v i = 0 v ( note 1 ) v o = v dd v dd = 5.0 v, f(x cin ) = 32 khz, f(x in ) = 8 mhz stck = f(x in )/4 v dd = 5.0 v f(x cin ) = 32 khz stck = f(x in ) v dd = 3.0 v, f(x cin ) = 32 khz, f(x in ) = 4 mhz stck = f(x in )/4 v dd = 3.0 v f(x cin ) = 32 khz stck = f(x in ) v dd = 5.0 v f(x in ) = stop f(x cin ) = 32 khz v dd = 3.0 v f(x in ) = stop f(x cin ) = 32 khz f(x in ) = stop f(x cin ) = 32 khz ta=25 c f(x in ) = stop f(x cin ) = 32 khz f(x in ) = stop, f(x cin ) = stop, ta = 25 c f(x in ) = stop, f(x cin ) = stop v dd = 5.0 v, v i = 0 v v dd = 3.0 v, v i = 0 v v dd = 5.0 v, v i = 0 v v dd = 3.0 v, v i = 0 v v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v impedance between v lc3 and v ss ta=25 c typ. 2.5 0.1 50 100 30 60 0.5 0.4 1.5 0.6 1.3 1.6 1.8 2.2 600 v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v at active high-speed mode while lcd is operating (seg 0 Cseg 15 ) at active low-speed mode while lcd is operating (seg 0 Cseg 15 ) at clock operating mode while lcd is operating (seg 0 Cseg 15 ) at ram back-up mode p0, p1 reset int reset f(x in ) = 2 mhz f(x in ) = 1 mhz f(x in ) = 1 mhz f(x in ) = 500 khz stck = f(x cin )/4 stck = f(x cin ) stck = f(x cin )/4 stck = f(x cin ) v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v min. 2.4 1.0 C1 20 40 12 25 300 2.3 1.4 0.7 0.6 0.4 70 90 30 40 27.5 10 notes 1: in this case, the pull-up transistor of port p1 is turned off and the port p2 function is selected by software. 2: the current value includes the current dissipation of the lcd power supply internal resistor (r vlc ). 3: v lc3 =v dd . 4.6 2.8 1.4 1.2 0.8 140 180 60 80 60 17.5 3.1 electrical characteristics
4551 group users manual appendix 3-5 3.1.4 basic timing diagram system clock port d output ports p0, p1 output ports p0, p1 and p2 input interrupt input stck parameter pin name machine cycle mi mi+1 int d 0 d 7 p0 0 p0 3 p1 0 p1 3 p0 0 p0 3 p1 0 p1 3 p2 0 p2 3 3.1 electrical characteristics
appendix 3-6 4551 group user?s manual 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3.2 typical characteristics (2) cpu high-speed operating (system clock: f(x in )/4) [measurement condition] x in : operating, x cin : 32 khz, timer 2 count source: x cin , system clock: f(x in )/4, lcd clock: 1 khz, duty: 1/4, bias: 1/3 ta = 25 ? c f(x in ) = 2 mhz 3.2 t ypical characteristics 3.2.1 v dd ei dd characteristics (1) cpu high-speed operating (system clock: f(x in )) [measurement condition] x in : operating, x cin : 32 khz, timer 2 count source: x cin , system clock: f(x in ), lcd clock: 1 khz, duty: 1/4, bias: 1/3 ta = 25? c f(x in ) = 1 mhz f(x in ) = 500 khz v dd (v) i dd (ma) v dd (v) i dd (ma) f(x in ) = 8 mhz f(x in ) = 4 mhz 0 1 3 4 5 6 0 1 3 4 5 6 2 7 7 2
4551 group users manual appendix 3-7 3.2 typical characteristics v dd (v) i dd ( m a) v dd (v) i dd ( m a) 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 (3) cpu low-speed operating (system clock: f(x cin )) [measurement condition] x in : stop, x cin : 32 khz, timer 2 count source: x cin , system clock: f(x cin ), lcd clock: 1 khz, duty: 1/4, bias: 1/3 ta = 25 c 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 (4) cpu low-speed operating (system clock: f(x cin )/4) [measurement condition] x in : stop, x cin : 32 khz, timer 2 count source: x cin , system clock: f(x cin )/4, lcd clock: 1 khz, duty: 1/4, bias: 1/3 ta = 25 c
appendix 3-8 4551 group users manual 3.2 typical characteristics v dd (v) i dd ( m a) (5) clock operating [measurement condition] x in : stop, x cin : 32 khz, timer 2 count source: x cin , system clock: stop, lcd clock: 1 khz, duty: 1/4, bias: 1/3 ta = 25 c 0 20 40 60 80 100 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
4551 group users manual appendix 3-9 3.2 typical characteristics 3.2.2 v oh Ci oh characteristics (port carr) (1) v dd = 3.0 v (2) v dd = 5.0 v -50.0 -45.0 -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0 0 3.0 2.7 2.4 2.1 1.8 1.5 v oh (v) i oh (ma) 1.2 0.9 0.6 0.3 -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0 0 5.0 4.5 4.0 3.5 3.0 2.5 v oh (v) i oh (ma) 2.0 1.5 1.0 0.5 ta = 25 oc ta = 25 oc
appendix 3-10 4551 group users manual 3.2.3 v ol Ci ol characteristics (ports p0, p1, d 0 Cd 7 , carr, reset ) (1) v dd = 3.0 v (2) v dd = 5.0 v 50.0 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0 0 3.0 2.7 2.4 2.1 1.8 1.5 v ol (v) i ol (ma) 1.2 0.9 0.6 0.3 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0 0 5.0 4.5 4.0 3.5 3.0 2.5 v ol (v) i ol (ma) 2.0 1.5 1.0 0.5 3.2 typical characteristics ta = 25 oc ta = 25 oc
4551 group users manual appendix 3-11 3.2.4 voltage drop detection circuit temperature characteristics (1) m34551mx-xxxfp (2) m34551e8-xxxfp 1 1.5 2 2.5 -20-10 0 10203040506070 1 1.5 2 2.5 -20-10 0 10203040506070 operating temperature range ( c) supply voltage (v) operating temperature range ( c) supply voltage (v) 3.2 typical characteristics
appendix 3-12 4551 group users manual 3.3 list of precautions 3.3 list of precautions noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; ? connect a bypass capacitor (approx. 0.1 m f) between pins v dd and v ss at the shortest distance, ? equalize its wiring in width and length, and ? use the thickest wire. in the built-in prom version, cnv ss pin is also used as v pp pin. accordingly, when using this pin, connect this pin to v ss through a resistor about 5 k w (connect this resistor to cnv ss / v pp pin as close as possible). prescaler stop the prescaler operation to change its frequency dividing ratio. a count source stop timer 1 or timer lc counting to change its count source. when timer 2 count source changes from f(x cin ) to orclk (w2 3 = 0 ? w2 3 = 1), the count value of timer 2 is initialized. however, when timer 2 count source changes from orclk to f(x cin ) (w2 3 = 1 ? w2 3 = 0) or the same count source is set again (w2 3 = 0 ? w2 3 = 0 or w2 3 = 1 ? w2 3 = 1), the count value of timer 2 is not initialized. ? timer 2 timer 2 has the watchdog timer function (wdt). when timer 2 is used as the wdt, note that the processing to initialize the count value and the execution of the wrst instruction. ? reading the count value stop the prescaler and then execute the tab1 instruction to read timer 1 data. ? writing to reload register r1 write the data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. ? notes when using the carrier wave output auto-control function ? execute the stcr instruction after setting the timer 1 and register c2 in order to start the carrier generating circuit operation. ? stop the timer 1 (w2 0 =0) after stopping the carrier generating circuit (spcr instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. ? if the carrier wave output auto-control function is invalidated (c2 0 =0) while the carrier wave output is auto-controlled, the output of port carr retains the state when the auto- control is invalidated regardless of timer 1 underflow. this state is released by timer 1 stop (w2 0 =0). when the carrier wave output auto-control function is validated (c2 0 =1) again after it is invalidated (c2 0 =0), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. however, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. ? use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto- control function is selected. if the orclk is used as the count source, a hazard may occur in port carr output because orclk is not synchronized with the carrier wave. ? when no carrier wave is selected with register c1 ((c1 3 c1 2 c1 1 c1 0 ) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function. ? d 5 /int pin when the interrupt valid waveform of d 5 /int pin is changed with the bit 2 of register i1 in software, be careful about the following notes. ? clear the bit 0 of register v1 to 0 and then change the interrupt valid waveform of d 5 /int pin with the bit 2 of register i1 (refer to figure 40 ). ? clear the bit 2 of register i1 to 0 and execute the snz0 instruction to clear the exf0 flag after executing at least one instruction (refer to figure 40 ). depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. la 4 ; ( 555 0 2 ) tv1a ; the snz0 instruction is valid la 4 ti1a ; change of the interrupt valid waveform nop snz0 ;the snz0 instruction is executed nop 5 : this bit is not related to the setting of int. . . . . . . one time prom version the operating power voltage of the one time prom version is within the range of 2.5 v to 5.5 v. multifunction note that the port d 5 output function can be used even when int function is selected. power down instruction (pof instruction, pof2 instruction) execute the pof or pof2 instruction immediately after executing the epof instruction to enter the power down state. note that system cannot enter the power down state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instrcution. program counter make sure that the pc h does not specify after the last page of the built-in rom. fig. 40 external 0 interrupt program example 12 11
4551 group users manual appendix 3-13 3.4 notes on noise 3.4 notes on noise countermeasures against noise are described below. the following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 shortest wiring length the wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) package select the smallest possible package to make the total wiring length short. l reason the wiring length depends on a microcom- puter package. use of a small package, for example qfp and not dip, makes the total wiring length short to reduce influence of noise. fig. 3.4.1 selection of packages (2) wiring for reset input pin make the length of wiring which is connected to the reset input pin as short as possible. especially, connect a capacitor across the reset input pin and the v ss pin with the shortest possible wiring (within 20mm). l reason the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset input pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. dip sdip sop qfp fig. 3.4.2 wiring for the reset input pin reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k.
appendix 3-14 4551 group users manual 3.4 notes on noise (3) wiring for clock input/output pins ? make the length of wiring which is connected to clock i/o pins as short as possible. ? make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for oscillation from other v ss patterns. fig. 3.4.3 wiring for clock i/o pins l reason if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig. 3.4.4 wiring for cnv ss pin noise x in x out v ss x in x out v ss n.g. o.k. noise cnv ss v ss cnv ss v ss n.g. o.k. (4) wiring to cnv ss pin connect the cnv ss pin to the v ss pin with the shortest possible wiring. l reason the processor mode of a microcomputer is influenced by a potential at the cnv ss pin. if a potential difference is caused by the noise between pins cnv ss and v ss , the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway.
4551 group users manual appendix 3-15 3.4 notes on noise (5) wiring to v pp pin of one time prom version l when the v pp pin is also used as the cnv ss pin connect an approximately 5 k w resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible (refer to figure 3.4.5 ) note: even when a circuit which included an approximately 5 k w resistor is used in the mask rom version, the microcomputer operates correctly. l reason the v pp pin of the one time prom ver- sion is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for writing flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal instruction codes or data are read from the built-in prom, which may cause a program runaway. fig. 3.4.5 wiring for the v pp pin of the one time prom version cnv ss /v pp when the v pp pin is also used as the cnv ss pin v ss in the shortest distance approximately 5k w 3.4.2 connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 m f bypass capacitor across the v ss line and the v cc line as follows: ? connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ? connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v cc line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. fig. 3.4.6 bypass capacitor across the v ss line and the v cc line v ss v cc aa aa aa aa aa aa v ss v cc aa aa aa aa aa aa aa aa aa aa n.g. o.k.
appendix 3-16 4551 group users manual 3.4 notes on noise 3.4.3 oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. l reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. fig. 3.4.7 wiring for a large current signal line (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. l reason signal lines where potential levels change frequently (such as the carr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. x in x out v ss m microcomputer mutual inductance large current gnd fig. 3.4.8 wiring to a signal line where potential levels change frequently (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. fig. 3.4.9 v ss pattern on the underside of an oscillator x in x out v ss cntr do not cross n.g. aaa aaa aaa aaa a a a aaa a a a a a aa aa x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines
4551 group users manual appendix 3-17 3.4 notes on noise 3.4.4 setup for i/o ports setup i/o ports using hardware and software as follows: ? connect a resistor of 100 w or more to an i/o port in series. ? as for an input port, read data several times by a program for checking whether input levels are equal or not. ? as for an output port or an i/o port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. ? rewrite data to pull-up control registers at fixed periods. 3.4.5 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. ? assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 3 as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. ? watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initial value n has been set. ? detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. ? decrements the swdt contents by 1 at each interrupt processing. ? determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). ? detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. (counts of interrupt processing executed in each main routine) fig. 3.4.10 watchdog timer by software main routine (swdt) ? n ei main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) ? (swdt)1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? 1 n
appendix 3-18 4551 group users manual ] 1. confirmation specify the type of eproms submitted. three sets of eproms are required for each pattern (check in the approximate box). if at least two of the three sets of eproms submitted contain the identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differ from this data. thus, the customer must be especially careful in verifying the data contained in the eproms submitted. checksum code for entire eprom area (hexadecimal notation) eprom type: company name date issued date: ] customer 27c256 27c512 low-order 5-bit data 123456789012345678901234 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 123456789012345678901234 high-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 0000 16 0fff 16 4000 16 4fff 16 7fff 16 4.00k 4.00k low-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 high-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 0000 16 0fff 16 4000 16 4fff 16 ffff 16 4.00k 4.00k set ff 16 in the shaded area. set 111 2 in the area of low-order and high-order 5-bit data. ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the approximate mark specification form (48p6s-a for m34551m4-xxxfp) and attach to the mask rom order confirmation form. ] 3. comments tel ( ) mask rom number date: section head signature supervisor signature responsible officer supervisor issuance s ignature receipt gzz-sh10-66b <63a0> 4500 series mask rom order confirmation form single-chip microcomputer m34551m4-xxxfp mitsubishi electric please fill in all items marked ] . 3.5 mask rom order confirmation form 3.5 mask rom order confirmation form
4551 group users manual appendix 3-19 ] 1. confirmation specify the type of eproms submitted. three sets of eproms are required for each pattern (check in the approximate box). if at least two of the three sets of eproms submitted contain the identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differ from this data. thus, the customer must be especially careful in verifying the data contained in the eproms submitted. checksum code for entire eprom area (hexadecimal notation) eprom type: company name date issued date: ] customer 27c256 27c512 low-order 5-bit data 123456789012345678901234 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 12345678901234567890123 4 123456789012345678901234 high-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 0000 16 1fff 16 4000 16 5fff 16 7fff 16 8.00k 8.00k low-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 high-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 0000 16 1fff 16 4000 16 5fff 16 ffff 16 8.00k 8.00k set ff 16 in the shaded area. set 111 2 in the area of low-order and high-order 5-bit data. ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the approximate mark specification form (48p6s-a for m34551m4-xxxfp) and attach to the mask rom order confirmation form. ] 3. comments tel ( ) mask rom number date: section head signature supervisor signature responsible officer supervisor issuance s ignature receipt gzz-sh52-94b <85a0> 4500 series mask rom order confirmation form single-chip microcomputer M34551M8-XXXFP mitsubishi electric please fill in all items marked ] . 3.5 mask rom order confirmation form
appendix 3-20 4551 group users manual ] 1. confirmation specify the type of eproms submitted. three sets of eproms are required for each pattern (check in the approximate box). if at least two of the three sets of eproms submitted contain the identical data, we will produce programming based on this data. we shall assume the responsibility for errors only if the rom data on the products we produce differ from this data. thus, the customer must be especially careful in verifying the data contained in the eproms submitted. checksum code for entire eprom area (hexadecimal notation) eprom type: date: ] customer rom number date: section head signature supervisor signature responsible officer supervisor issuance s ignature receipt tel ( ) 27c256 27c512 low-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 high-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 0000 16 1fff 16 4000 16 5fff 16 7fff 16 8.00k 8.00k low-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 high-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 0000 16 1fff 16 4000 16 5fff 16 ffff 16 set ff 16 in the shaded area. set 111 2 in the area of low-order and high-order 5-bit data. ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the approximate mark specification form (48p6s-a for m34551e8-xxxfp) and attach to the rom programming order confirmation form. ] 3. comments gzz-sh10-69b <64a0> 4500 series rom programming order confirmation form single-chip microcomputer m34551e8-xxxfp mitsubishi electric please fill in all items marked ] . company name date issued 3.6 rom programming order confirmation form 3.6 rom programming order confirmation form 8.00k 8.00k
4551 group users manual appendix 3-21 3.7 mark specification form 3.7 mark specification form customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name notes 1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 9 characters: only 0 to 9, a to z, +, C, /, (, ), &, , . (periods), , (commas) are usable. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 48p6s-a (48-pin qfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (if neede d). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi ic catalog name notes1 :if special mark is to be printed, indicate the desired lay- out of the mark in the left figure. the layout will be duplicated technically as close as possible. mitsubishi lot number (6-digit, or 7-digit) and mask rom number (3-digit) are always marked. 2 : if the cunstomers trade mark logo must be used in the special mark, check the box below. please submit a clean original of the logo. for the new special character fonts, a clean font original (ideally logo drawing) must be submitted. special logo required 1 48 39 24 38 25 15 14 mitsubishi ic catalog name mitsubishi lot number (6-digit or 7-digit) mitsubishi ic catalog name 1 48 39 24 38 25 15 14 mitsubishi lot number (6-digit or 7-digit) 1 48 39 24 38 25 15 14
appendix 3-22 4551 group users manual 3.8 package outline 3.8 package outline qfp48-p-710-0.65 0.29 weight(g) jedec code eiaj package code lead material alloy 42 48p6s-a plastic 48pin 7 5 10mm body qfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.35 i 2 1.0 m d 7.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.3 12.0 11.7 9.3 9.0 8.7 0.65 10.2 10.0 9.8 7.2 7.0 6.8 0.2 0.15 0.13 0.35 0.25 0.2 1.85 0 2.15 e e e e c h e 1 48 39 24 38 25 15 14 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f
mitsubishi semiconductors users manual 4551 group sep. first edition 1998 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1998 mitsubishi electric corporation
mitsubishi electric corporation head office: mitsubishi denki bldg., marunouchi, tokyo 100. telex: j24532 cable: melco tokyo users manual 4551 group ? 1998 mitsubishi electric corporation. new publication, effective jul. 1997. specifications subject to change without notice.
rev. rev. no. date 1.0 first edition 980930 revision description list 4551 group users manual (1/1) revision description

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